tlb.c 2.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576
  1. /*
  2. * Copyright 2008 Freescale Semiconductor, Inc.
  3. *
  4. * (C) Copyright 2000
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <asm/mmu.h>
  27. struct fsl_e_tlb_entry tlb_table[] = {
  28. /* TLB 0 - for temp stack in cache */
  29. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  30. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  31. 0, 0, BOOKE_PAGESZ_4K, 0),
  32. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  33. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  34. 0, 0, BOOKE_PAGESZ_4K, 0),
  35. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  36. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  37. 0, 0, BOOKE_PAGESZ_4K, 0),
  38. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  39. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  40. 0, 0, BOOKE_PAGESZ_4K, 0),
  41. SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
  42. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  43. 0, 0, BOOKE_PAGESZ_4K, 0),
  44. /* TLB 1 */
  45. /* *I*G* - CCSRBAR */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  47. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48. 0, 0, BOOKE_PAGESZ_1M, 1),
  49. /* W**G* - Flash/promjet, localbus */
  50. /* This will be changed to *I*G* after relocation to RAM. */
  51. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  52. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  53. 0, 1, BOOKE_PAGESZ_256M, 1),
  54. /* *I*G* - PCI */
  55. SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
  56. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57. 0, 2, BOOKE_PAGESZ_1G, 1),
  58. /* *I*G* - PCI I/O */
  59. SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
  60. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61. 0, 3, BOOKE_PAGESZ_256K, 1),
  62. /* *I*G - NAND */
  63. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  64. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65. 0, 4, BOOKE_PAGESZ_1M, 1),
  66. };
  67. int num_tlb_entries = ARRAY_SIZE(tlb_table);