zmx25.c 6.7 KB

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  1. /*
  2. * (c) 2011 Graf-Syteco, Matthias Weisser
  3. * <weisserm@arcor.de>
  4. *
  5. * Based on tx25.c:
  6. * (C) Copyright 2009 DENX Software Engineering
  7. * Author: John Rigby <jrigby@gmail.com>
  8. *
  9. * Based on imx27lite.c:
  10. * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
  11. * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
  12. * And:
  13. * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. *
  30. */
  31. #include <common.h>
  32. #include <mxc_gpio.h>
  33. #include <asm/io.h>
  34. #include <asm/arch/imx-regs.h>
  35. #include <asm/arch/imx25-pinmux.h>
  36. DECLARE_GLOBAL_DATA_PTR;
  37. int board_init()
  38. {
  39. struct iomuxc_mux_ctl *muxctl;
  40. struct iomuxc_pad_ctl *padctl;
  41. struct iomuxc_pad_input_select *inputselect;
  42. u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
  43. u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
  44. u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
  45. u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
  46. u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
  47. u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
  48. icache_enable();
  49. muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
  50. padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
  51. inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
  52. /* Setup of core volatage selection pin to run at 1.4V */
  53. writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
  54. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT);
  55. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1);
  56. /* Setup of input daisy chains for SD card pins*/
  57. writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
  58. writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
  59. writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
  60. writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
  61. writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
  62. writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
  63. /* Setup of digital output for USB power and OC */
  64. writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
  65. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT);
  66. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1);
  67. writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
  68. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN);
  69. /* Setup of digital output control pins */
  70. writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
  71. writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
  72. writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
  73. writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
  74. writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
  75. writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
  76. /* Switch both output drivers off */
  77. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0);
  78. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT);
  79. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0);
  80. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT);
  81. /* Setup of key input pin GPIO2[29]*/
  82. writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
  83. writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
  84. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN);
  85. /* Setup of status LED outputs */
  86. writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
  87. writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
  88. /* Switch both LEDs off */
  89. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
  90. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT);
  91. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
  92. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT);
  93. /* Setup of CAN1 and CAN2 signals */
  94. writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
  95. writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
  96. writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
  97. writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
  98. /* Setup of input daisy chains for CAN signals*/
  99. writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
  100. writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
  101. /* Setup of I2C3 signals */
  102. writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
  103. writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
  104. /* Setup of input daisy chains for I2C3 signals*/
  105. writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
  106. writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
  107. /* board id for linux */
  108. gd->bd->bi_arch_number = MACH_TYPE_ZMX25;
  109. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  110. return 0;
  111. }
  112. int board_late_init(void)
  113. {
  114. const char *e;
  115. #ifdef CONFIG_FEC_MXC
  116. struct iomuxc_mux_ctl *muxctl;
  117. struct iomuxc_pad_ctl *padctl;
  118. u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
  119. u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
  120. /*
  121. * fec pin init is generic
  122. */
  123. mx25_fec_init_pins();
  124. /*
  125. * Set up LAN-RESET and FEC_RX_ERR
  126. *
  127. * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
  128. * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
  129. */
  130. muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
  131. padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
  132. writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
  133. writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
  134. /* assert PHY reset (low) */
  135. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0);
  136. mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT);
  137. udelay(5000);
  138. /* deassert PHY reset */
  139. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1);
  140. udelay(5000);
  141. #endif
  142. e = getenv("gs_base_board");
  143. if (e != NULL) {
  144. if (strcmp(e, "G283") == 0) {
  145. int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29));
  146. if (key) {
  147. /* Switch on both LEDs to inidcate boot mode */
  148. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
  149. mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
  150. setenv("preboot", "run gs_slow_boot");
  151. } else
  152. setenv("preboot", "run gs_fast_boot");
  153. }
  154. }
  155. return 0;
  156. }
  157. int dram_init(void)
  158. {
  159. /* dram_init must store complete ramsize in gd->ram_size */
  160. gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
  161. PHYS_SDRAM_SIZE);
  162. return 0;
  163. }
  164. void dram_init_banksize(void)
  165. {
  166. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  167. gd->bd->bi_dram[0].size = gd->ram_size;
  168. }