tx25.c 4.7 KB

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  1. /*
  2. * (C) Copyright 2009 DENX Software Engineering
  3. * Author: John Rigby <jrigby@gmail.com>
  4. *
  5. * Based on imx27lite.c:
  6. * Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
  7. * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
  8. * And:
  9. * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. *
  26. */
  27. #include <common.h>
  28. #include <asm/io.h>
  29. #include <asm/arch/imx-regs.h>
  30. #include <asm/arch/imx25-pinmux.h>
  31. static void mdelay(int n)
  32. {
  33. while (n-- > 0)
  34. udelay(1000);
  35. }
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #ifdef CONFIG_FEC_MXC
  38. void tx25_fec_init(void)
  39. {
  40. struct iomuxc_mux_ctl *muxctl;
  41. struct iomuxc_pad_ctl *padctl;
  42. u32 val;
  43. u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
  44. struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE;
  45. struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE;
  46. u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode;
  47. debug("tx25_fec_init\n");
  48. /*
  49. * fec pin init is generic
  50. */
  51. mx25_fec_init_pins();
  52. /*
  53. * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
  54. *
  55. * FEC_RESET_B: gpio4[7] is ALT 5 mode of pin D13
  56. * FEC_ENABLE_B: gpio4[9] is ALT 5 mode of pin D11
  57. */
  58. muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
  59. padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
  60. writel(gpio_mux_mode, &muxctl->pad_d13);
  61. writel(gpio_mux_mode, &muxctl->pad_d11);
  62. writel(0x0, &padctl->pad_d13);
  63. writel(0x0, &padctl->pad_d11);
  64. /* drop PHY power and assert reset (low) */
  65. val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9));
  66. writel(val, &gpio4->gpio_dr);
  67. val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9);
  68. writel(val, &gpio4->gpio_dir);
  69. mdelay(5);
  70. debug("resetting phy\n");
  71. /* turn on PHY power leaving reset asserted */
  72. val = readl(&gpio4->gpio_dr) | 1 << 9;
  73. writel(val, &gpio4->gpio_dr);
  74. mdelay(10);
  75. /*
  76. * Setup some strapping pins that are latched by the PHY
  77. * as reset goes high.
  78. *
  79. * Set PHY mode to 111
  80. * mode0 comes from FEC_RDATA0 which is GPIO 3_10 in mux mode 5
  81. * mode1 comes from FEC_RDATA1 which is GPIO 3_11 in mux mode 5
  82. * mode2 is tied high so nothing to do
  83. *
  84. * Turn on RMII mode
  85. * RMII mode is selected by FEC_RX_DV which is GPIO 3_12 in mux mode
  86. */
  87. /*
  88. * save three current mux modes and set each to gpio mode
  89. */
  90. saved_rdata0_mode = readl(&muxctl->pad_fec_rdata0);
  91. saved_rdata1_mode = readl(&muxctl->pad_fec_rdata1);
  92. saved_rx_dv_mode = readl(&muxctl->pad_fec_rx_dv);
  93. writel(gpio_mux_mode, &muxctl->pad_fec_rdata0);
  94. writel(gpio_mux_mode, &muxctl->pad_fec_rdata1);
  95. writel(gpio_mux_mode, &muxctl->pad_fec_rx_dv);
  96. /*
  97. * set each to 1 and make each an output
  98. */
  99. val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12);
  100. writel(val, &gpio3->gpio_dr);
  101. val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12);
  102. writel(val, &gpio3->gpio_dir);
  103. mdelay(22); /* this value came from RedBoot */
  104. /*
  105. * deassert PHY reset
  106. */
  107. val = readl(&gpio4->gpio_dr) | 1 << 7;
  108. writel(val, &gpio4->gpio_dr);
  109. writel(val, &gpio4->gpio_dr);
  110. mdelay(5);
  111. /*
  112. * set FEC pins back
  113. */
  114. writel(saved_rdata0_mode, &muxctl->pad_fec_rdata0);
  115. writel(saved_rdata1_mode, &muxctl->pad_fec_rdata1);
  116. writel(saved_rx_dv_mode, &muxctl->pad_fec_rx_dv);
  117. }
  118. #else
  119. #define tx25_fec_init()
  120. #endif
  121. int board_init()
  122. {
  123. #ifdef CONFIG_MXC_UART
  124. extern void mx25_uart1_init_pins(void);
  125. mx25_uart1_init_pins();
  126. #endif
  127. /* board id for linux */
  128. gd->bd->bi_arch_number = MACH_TYPE_TX25;
  129. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  130. return 0;
  131. }
  132. int board_late_init(void)
  133. {
  134. tx25_fec_init();
  135. return 0;
  136. }
  137. int dram_init (void)
  138. {
  139. /* dram_init must store complete ramsize in gd->ram_size */
  140. gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
  141. PHYS_SDRAM_1_SIZE);
  142. return 0;
  143. }
  144. void dram_init_banksize(void)
  145. {
  146. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  147. gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
  148. PHYS_SDRAM_1_SIZE);
  149. #if CONFIG_NR_DRAM_BANKS > 1
  150. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  151. gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
  152. PHYS_SDRAM_2_SIZE);
  153. #else
  154. #endif
  155. }
  156. int checkboard(void)
  157. {
  158. printf("KARO TX25\n");
  159. return 0;
  160. }