usb.c 6.0 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. /*
  25. * USB test
  26. *
  27. * The USB controller is tested in the local loopback mode.
  28. * It is configured so that endpoint 0 operates as host and endpoint 1
  29. * operates as function endpoint. After that an IN token transaction
  30. * is performed.
  31. * Refer to MPC850 User Manual, Section 32.11.1 USB Host Controller
  32. * Initialization Example.
  33. */
  34. #include <post.h>
  35. #if CONFIG_POST & CONFIG_SYS_POST_USB
  36. #include <commproc.h>
  37. #include <command.h>
  38. #define TOUT_LOOP 100
  39. #define PROFF_USB ((uint)0x0000)
  40. #define CPM_USB_EP0_BASE 0x0a00
  41. #define CPM_USB_EP1_BASE 0x0a20
  42. #define CPM_USB_DT0_BASE 0x0a80
  43. #define CPM_USB_DT1_BASE 0x0a90
  44. #define CPM_USB_DR0_BASE 0x0aa0
  45. #define CPM_USB_DR1_BASE 0x0ab0
  46. #define CPM_USB_RX0_BASE 0x0b00
  47. #define CPM_USB_RX1_BASE 0x0b08
  48. #define CPM_USB_TX0_BASE 0x0b20
  49. #define CPM_USB_TX1_BASE 0x0b28
  50. #define USB_EXPECT(x) if (!(x)) goto Done;
  51. typedef struct usb_param {
  52. ushort ep0ptr;
  53. ushort ep1ptr;
  54. ushort ep2ptr;
  55. ushort ep3ptr;
  56. uint rstate;
  57. uint rptr;
  58. ushort frame_n;
  59. ushort rbcnt;
  60. ushort rtemp;
  61. } usb_param_t;
  62. typedef struct usb_param_block {
  63. ushort rbase;
  64. ushort tbase;
  65. uchar rfcr;
  66. uchar tfcr;
  67. ushort mrblr;
  68. ushort rbptr;
  69. ushort tbptr;
  70. uint tstate;
  71. uint tptr;
  72. ushort tcrc;
  73. ushort tbcnt;
  74. uint res[2];
  75. } usb_param_block_t;
  76. typedef struct usb {
  77. uchar usmod;
  78. uchar usadr;
  79. uchar uscom;
  80. uchar res1;
  81. ushort usep[4];
  82. uchar res2[4];
  83. ushort usber;
  84. uchar res3[2];
  85. ushort usbmr;
  86. uchar res4;
  87. uchar usbs;
  88. uchar res5[8];
  89. } usb_t;
  90. int usb_post_test (int flags)
  91. {
  92. int res = -1;
  93. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  94. volatile cpm8xx_t *cp = &(im->im_cpm);
  95. volatile usb_param_t *pram_ptr;
  96. uint dpram;
  97. ushort DPRAM;
  98. volatile cbd_t *tx;
  99. volatile cbd_t *rx;
  100. volatile usb_t *usbr;
  101. volatile usb_param_block_t *ep0;
  102. volatile usb_param_block_t *ep1;
  103. int j;
  104. pram_ptr = (usb_param_t *) & (im->im_cpm.cp_dparam[PROFF_USB]);
  105. dpram = (uint) im->im_cpm.cp_dpmem;
  106. DPRAM = dpram;
  107. tx = (cbd_t *) (dpram + CPM_USB_TX0_BASE);
  108. rx = (cbd_t *) (dpram + CPM_USB_RX0_BASE);
  109. ep0 = (usb_param_block_t *) (dpram + CPM_USB_EP0_BASE);
  110. ep1 = (usb_param_block_t *) (dpram + CPM_USB_EP1_BASE);
  111. usbr = (usb_t *) & (im->im_cpm.cp_scc[0]);
  112. /* 01 */
  113. im->im_ioport.iop_padir &= ~(ushort) 0x0200;
  114. im->im_ioport.iop_papar |= (ushort) 0x0200;
  115. cp->cp_sicr &= ~0x000000FF;
  116. cp->cp_sicr |= 0x00000018;
  117. cp->cp_brgc4 = 0x00010001;
  118. /* 02 */
  119. im->im_ioport.iop_padir &= ~(ushort) 0x0002;
  120. im->im_ioport.iop_padir &= ~(ushort) 0x0001;
  121. im->im_ioport.iop_papar |= (ushort) 0x0002;
  122. im->im_ioport.iop_papar |= (ushort) 0x0001;
  123. /* 03 */
  124. im->im_ioport.iop_pcdir &= ~(ushort) 0x0020;
  125. im->im_ioport.iop_pcdir &= ~(ushort) 0x0010;
  126. im->im_ioport.iop_pcpar &= ~(ushort) 0x0020;
  127. im->im_ioport.iop_pcpar &= ~(ushort) 0x0010;
  128. im->im_ioport.iop_pcso |= (ushort) 0x0020;
  129. im->im_ioport.iop_pcso |= (ushort) 0x0010;
  130. /* 04 */
  131. im->im_ioport.iop_pcdir |= (ushort) 0x0200;
  132. im->im_ioport.iop_pcdir |= (ushort) 0x0100;
  133. im->im_ioport.iop_pcpar |= (ushort) 0x0200;
  134. im->im_ioport.iop_pcpar |= (ushort) 0x0100;
  135. /* 05 */
  136. pram_ptr->frame_n = 0;
  137. /* 06 */
  138. pram_ptr->ep0ptr = DPRAM + CPM_USB_EP0_BASE;
  139. pram_ptr->ep1ptr = DPRAM + CPM_USB_EP1_BASE;
  140. /* 07-10 */
  141. tx[0].cbd_sc = 0xB800;
  142. tx[0].cbd_datlen = 3;
  143. tx[0].cbd_bufaddr = dpram + CPM_USB_DT0_BASE;
  144. tx[1].cbd_sc = 0xBC80;
  145. tx[1].cbd_datlen = 3;
  146. tx[1].cbd_bufaddr = dpram + CPM_USB_DT1_BASE;
  147. rx[0].cbd_sc = 0xA000;
  148. rx[0].cbd_datlen = 0;
  149. rx[0].cbd_bufaddr = dpram + CPM_USB_DR0_BASE;
  150. rx[1].cbd_sc = 0xA000;
  151. rx[1].cbd_datlen = 0;
  152. rx[1].cbd_bufaddr = dpram + CPM_USB_DR1_BASE;
  153. /* 11-12 */
  154. *(volatile int *) (dpram + CPM_USB_DT0_BASE) = 0x69856000;
  155. *(volatile int *) (dpram + CPM_USB_DT1_BASE) = 0xABCD1234;
  156. *(volatile int *) (dpram + CPM_USB_DR0_BASE) = 0;
  157. *(volatile int *) (dpram + CPM_USB_DR1_BASE) = 0;
  158. /* 13-16 */
  159. ep0->rbase = DPRAM + CPM_USB_RX0_BASE;
  160. ep0->tbase = DPRAM + CPM_USB_TX0_BASE;
  161. ep0->rfcr = 0x18;
  162. ep0->tfcr = 0x18;
  163. ep0->mrblr = 0x100;
  164. ep0->rbptr = DPRAM + CPM_USB_RX0_BASE;
  165. ep0->tbptr = DPRAM + CPM_USB_TX0_BASE;
  166. ep0->tstate = 0;
  167. /* 17-20 */
  168. ep1->rbase = DPRAM + CPM_USB_RX1_BASE;
  169. ep1->tbase = DPRAM + CPM_USB_TX1_BASE;
  170. ep1->rfcr = 0x18;
  171. ep1->tfcr = 0x18;
  172. ep1->mrblr = 0x100;
  173. ep1->rbptr = DPRAM + CPM_USB_RX1_BASE;
  174. ep1->tbptr = DPRAM + CPM_USB_TX1_BASE;
  175. ep1->tstate = 0;
  176. /* 21-24 */
  177. usbr->usep[0] = 0x0000;
  178. usbr->usep[1] = 0x1100;
  179. usbr->usep[2] = 0x2200;
  180. usbr->usep[3] = 0x3300;
  181. /* 25 */
  182. usbr->usmod = 0x06;
  183. /* 26 */
  184. usbr->usadr = 0x05;
  185. /* 27 */
  186. usbr->uscom = 0;
  187. /* 28 */
  188. usbr->usmod |= 0x01;
  189. udelay (1);
  190. /* 29-30 */
  191. usbr->uscom = 0x80;
  192. usbr->uscom = 0x81;
  193. /* Wait for the data packet to be transmitted */
  194. for (j = 0; j < TOUT_LOOP; j++) {
  195. if (tx[1].cbd_sc & (ushort) 0x8000)
  196. udelay (1);
  197. else
  198. break;
  199. }
  200. USB_EXPECT (j < TOUT_LOOP);
  201. USB_EXPECT (tx[0].cbd_sc == 0x3800);
  202. USB_EXPECT (tx[0].cbd_datlen == 3);
  203. USB_EXPECT (tx[1].cbd_sc == 0x3C80);
  204. USB_EXPECT (tx[1].cbd_datlen == 3);
  205. USB_EXPECT (rx[0].cbd_sc == 0x2C00);
  206. USB_EXPECT (rx[0].cbd_datlen == 5);
  207. USB_EXPECT (*(volatile int *) (dpram + CPM_USB_DR0_BASE) ==
  208. 0xABCD122B);
  209. USB_EXPECT (*(volatile char *) (dpram + CPM_USB_DR0_BASE + 4) == 0x42);
  210. res = 0;
  211. Done:
  212. return res;
  213. }
  214. #endif /* CONFIG_POST & CONFIG_SYS_POST_USB */