cfi_flash.c 28 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
  4. *
  5. * Copyright (C) 2003 Arabella Software Ltd.
  6. * Yuli Barcohen <yuli@arabellasw.com>
  7. * Modified to work with AMD flashes
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. *
  27. * History
  28. * 01/20/2004 - combined variants of original driver.
  29. *
  30. * Tested Architectures
  31. * Port Width Chip Width # of banks Flash Chip Board
  32. * 32 16 1 23F128J3 seranoa/eagle
  33. *
  34. */
  35. /* The DEBUG define must be before common to enable debugging */
  36. #undef DEBUG
  37. #include <common.h>
  38. #include <asm/processor.h>
  39. #ifdef CFG_FLASH_CFI_DRIVER
  40. /*
  41. * This file implements a Common Flash Interface (CFI) driver for U-Boot.
  42. * The width of the port and the width of the chips are determined at initialization.
  43. * These widths are used to calculate the address for access CFI data structures.
  44. * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
  45. *
  46. * References
  47. * JEDEC Standard JESD68 - Common Flash Interface (CFI)
  48. * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
  49. * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
  50. * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
  51. *
  52. * TODO
  53. *
  54. * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
  55. * Table (ALT) to determine if protection is available
  56. *
  57. * Add support for other command sets Use the PRI and ALT to determine command set
  58. * Verify erase and program timeouts.
  59. */
  60. #define FLASH_CMD_CFI 0x98
  61. #define FLASH_CMD_READ_ID 0x90
  62. #define FLASH_CMD_RESET 0xff
  63. #define FLASH_CMD_BLOCK_ERASE 0x20
  64. #define FLASH_CMD_ERASE_CONFIRM 0xD0
  65. #define FLASH_CMD_WRITE 0x40
  66. #define FLASH_CMD_PROTECT 0x60
  67. #define FLASH_CMD_PROTECT_SET 0x01
  68. #define FLASH_CMD_PROTECT_CLEAR 0xD0
  69. #define FLASH_CMD_CLEAR_STATUS 0x50
  70. #define FLASH_CMD_WRITE_TO_BUFFER 0xE8
  71. #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
  72. #define FLASH_STATUS_DONE 0x80
  73. #define FLASH_STATUS_ESS 0x40
  74. #define FLASH_STATUS_ECLBS 0x20
  75. #define FLASH_STATUS_PSLBS 0x10
  76. #define FLASH_STATUS_VPENS 0x08
  77. #define FLASH_STATUS_PSS 0x04
  78. #define FLASH_STATUS_DPS 0x02
  79. #define FLASH_STATUS_R 0x01
  80. #define FLASH_STATUS_PROTECT 0x01
  81. #define AMD_CMD_RESET 0xF0
  82. #define AMD_CMD_WRITE 0xA0
  83. #define AMD_CMD_ERASE_START 0x80
  84. #define AMD_CMD_ERASE_SECTOR 0x30
  85. #define AMD_STATUS_TOGGLE 0x40
  86. #define AMD_STATUS_ERROR 0x20
  87. #define FLASH_OFFSET_CFI 0x55
  88. #define FLASH_OFFSET_CFI_RESP 0x10
  89. #define FLASH_OFFSET_PRIMARY_VENDOR 0x13
  90. #define FLASH_OFFSET_WTOUT 0x1F
  91. #define FLASH_OFFSET_WBTOUT 0x20
  92. #define FLASH_OFFSET_ETOUT 0x21
  93. #define FLASH_OFFSET_CETOUT 0x22
  94. #define FLASH_OFFSET_WMAX_TOUT 0x23
  95. #define FLASH_OFFSET_WBMAX_TOUT 0x24
  96. #define FLASH_OFFSET_EMAX_TOUT 0x25
  97. #define FLASH_OFFSET_CEMAX_TOUT 0x26
  98. #define FLASH_OFFSET_SIZE 0x27
  99. #define FLASH_OFFSET_INTERFACE 0x28
  100. #define FLASH_OFFSET_BUFFER_SIZE 0x2A
  101. #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
  102. #define FLASH_OFFSET_ERASE_REGIONS 0x2D
  103. #define FLASH_OFFSET_PROTECT 0x02
  104. #define FLASH_OFFSET_USER_PROTECTION 0x85
  105. #define FLASH_OFFSET_INTEL_PROTECTION 0x81
  106. #define FLASH_MAN_CFI 0x01000000
  107. #define CFI_CMDSET_NONE 0
  108. #define CFI_CMDSET_INTEL_EXTENDED 1
  109. #define CFI_CMDSET_AMD_STANDARD 2
  110. #define CFI_CMDSET_INTEL_STANDARD 3
  111. #define CFI_CMDSET_AMD_EXTENDED 4
  112. #define CFI_CMDSET_MITSU_STANDARD 256
  113. #define CFI_CMDSET_MITSU_EXTENDED 257
  114. #define CFI_CMDSET_SST 258
  115. typedef union {
  116. unsigned char c;
  117. unsigned short w;
  118. unsigned long l;
  119. unsigned long long ll;
  120. } cfiword_t;
  121. typedef union {
  122. volatile unsigned char *cp;
  123. volatile unsigned short *wp;
  124. volatile unsigned long *lp;
  125. volatile unsigned long long *llp;
  126. } cfiptr_t;
  127. #define NUM_ERASE_REGIONS 4
  128. static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
  129. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  130. /*-----------------------------------------------------------------------
  131. * Functions
  132. */
  133. typedef unsigned long flash_sect_t;
  134. static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
  135. static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
  136. static void flash_write_cmd(flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  137. static void flash_unlock_seq(flash_info_t *info);
  138. static int flash_isequal(flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  139. static int flash_isset(flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  140. static int flash_toggle(flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
  141. static int flash_detect_cfi(flash_info_t * info);
  142. static ulong flash_get_size (ulong base, int banknum);
  143. static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
  144. static int flash_full_status_check(flash_info_t * info, flash_sect_t sector, ulong tout, char * prompt);
  145. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  146. static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
  147. #endif
  148. #ifdef DEBUG
  149. void print_longlong(char * str, unsigned long long data)
  150. {
  151. int i;
  152. char *cp;
  153. cp = (unsigned char *)&data;
  154. for(i=0;i<8; i++)
  155. sprintf(&str[i*2], "%2.2x", *cp++);
  156. }
  157. #endif
  158. /*-----------------------------------------------------------------------
  159. * create an address based on the offset and the port width
  160. */
  161. inline uchar * flash_make_addr(flash_info_t * info, flash_sect_t sect, uint offset)
  162. {
  163. return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
  164. }
  165. /*-----------------------------------------------------------------------
  166. * read a character at a port width address
  167. */
  168. inline uchar flash_read_uchar(flash_info_t * info, uint offset)
  169. {
  170. uchar *cp;
  171. cp = flash_make_addr(info, 0, offset);
  172. return (cp[info->portwidth - 1]);
  173. }
  174. /*-----------------------------------------------------------------------
  175. * read a short word by swapping for ppc format.
  176. */
  177. ushort flash_read_ushort(flash_info_t * info, flash_sect_t sect, uint offset)
  178. {
  179. uchar * addr;
  180. addr = flash_make_addr(info, sect, offset);
  181. return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
  182. }
  183. /*-----------------------------------------------------------------------
  184. * read a long word by picking the least significant byte of each maiximum
  185. * port size word. Swap for ppc format.
  186. */
  187. ulong flash_read_long(flash_info_t * info, flash_sect_t sect, uint offset)
  188. {
  189. uchar * addr;
  190. addr = flash_make_addr(info, sect, offset);
  191. return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
  192. (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
  193. }
  194. /*-----------------------------------------------------------------------
  195. */
  196. unsigned long flash_init (void)
  197. {
  198. unsigned long size = 0;
  199. int i;
  200. /* Init: no FLASHes known */
  201. for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
  202. flash_info[i].flash_id = FLASH_UNKNOWN;
  203. size += flash_info[i].size = flash_get_size(bank_base[i], i);
  204. if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  205. printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
  206. i, flash_info[i].size, flash_info[i].size << 20);
  207. }
  208. }
  209. /* Monitor protection ON by default */
  210. #if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
  211. flash_protect(FLAG_PROTECT_SET,
  212. CFG_MONITOR_BASE,
  213. CFG_MONITOR_BASE + monitor_flash_len - 1,
  214. &flash_info[0]);
  215. #endif
  216. return (size);
  217. }
  218. /*-----------------------------------------------------------------------
  219. */
  220. int flash_erase (flash_info_t *info, int s_first, int s_last)
  221. {
  222. int rcode = 0;
  223. int prot;
  224. flash_sect_t sect;
  225. if( info->flash_id != FLASH_MAN_CFI) {
  226. printf ("Can't erase unknown flash type - aborted\n");
  227. return 1;
  228. }
  229. if ((s_first < 0) || (s_first > s_last)) {
  230. printf ("- no sectors to erase\n");
  231. return 1;
  232. }
  233. prot = 0;
  234. for (sect=s_first; sect<=s_last; ++sect) {
  235. if (info->protect[sect]) {
  236. prot++;
  237. }
  238. }
  239. if (prot) {
  240. printf ("- Warning: %d protected sectors will not be erased!\n",
  241. prot);
  242. } else {
  243. printf ("\n");
  244. }
  245. for (sect = s_first; sect<=s_last; sect++) {
  246. if (info->protect[sect] == 0) { /* not protected */
  247. switch(info->vendor) {
  248. case CFI_CMDSET_INTEL_STANDARD:
  249. case CFI_CMDSET_INTEL_EXTENDED:
  250. flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
  251. flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
  252. flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
  253. break;
  254. case CFI_CMDSET_AMD_STANDARD:
  255. case CFI_CMDSET_AMD_EXTENDED:
  256. flash_unlock_seq(info);
  257. flash_write_cmd(info, sect, 0x555, AMD_CMD_ERASE_START);
  258. flash_unlock_seq(info);
  259. flash_write_cmd(info, sect, 0, AMD_CMD_ERASE_SECTOR);
  260. break;
  261. default:
  262. debug("Unkown flash vendor %d\n", info->vendor);
  263. break;
  264. }
  265. if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
  266. rcode = 1;
  267. } else
  268. printf(".");
  269. }
  270. }
  271. printf (" done\n");
  272. return rcode;
  273. }
  274. /*-----------------------------------------------------------------------
  275. */
  276. void flash_print_info (flash_info_t *info)
  277. {
  278. int i;
  279. if (info->flash_id != FLASH_MAN_CFI) {
  280. printf ("missing or unknown FLASH type\n");
  281. return;
  282. }
  283. printf("CFI conformant FLASH (%d x %d)",
  284. (info->portwidth << 3 ), (info->chipwidth << 3 ));
  285. printf (" Size: %ld MB in %d Sectors\n",
  286. info->size >> 20, info->sector_count);
  287. printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
  288. info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
  289. printf (" Sector Start Addresses:");
  290. for (i=0; i<info->sector_count; ++i) {
  291. #ifdef CFG_FLASH_EMPTY_INFO
  292. int k;
  293. int size;
  294. int erased;
  295. volatile unsigned long *flash;
  296. /*
  297. * Check if whole sector is erased
  298. */
  299. if (i != (info->sector_count-1))
  300. size = info->start[i+1] - info->start[i];
  301. else
  302. size = info->start[0] + info->size - info->start[i];
  303. erased = 1;
  304. flash = (volatile unsigned long *)info->start[i];
  305. size = size >> 2; /* divide by 4 for longword access */
  306. for (k=0; k<size; k++)
  307. {
  308. if (*flash++ != 0xffffffff)
  309. {
  310. erased = 0;
  311. break;
  312. }
  313. }
  314. if ((i % 5) == 0)
  315. printf ("\n");
  316. /* print empty and read-only info */
  317. printf (" %08lX%s%s",
  318. info->start[i],
  319. erased ? " E" : " ",
  320. info->protect[i] ? "RO " : " ");
  321. #else
  322. if ((i % 5) == 0)
  323. printf ("\n ");
  324. printf (" %08lX%s",
  325. info->start[i],
  326. info->protect[i] ? " (RO)" : " ");
  327. #endif
  328. }
  329. printf ("\n");
  330. return;
  331. }
  332. /*-----------------------------------------------------------------------
  333. * Copy memory to flash, returns:
  334. * 0 - OK
  335. * 1 - write timeout
  336. * 2 - Flash not erased
  337. */
  338. int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  339. {
  340. ulong wp;
  341. ulong cp;
  342. int aln;
  343. cfiword_t cword;
  344. int i, rc;
  345. /* get lower aligned address */
  346. wp = (addr & ~(info->portwidth - 1));
  347. /* handle unaligned start */
  348. if((aln = addr - wp) != 0) {
  349. cword.l = 0;
  350. cp = wp;
  351. for(i=0;i<aln; ++i, ++cp)
  352. flash_add_byte(info, &cword, (*(uchar *)cp));
  353. for(; (i< info->portwidth) && (cnt > 0) ; i++) {
  354. flash_add_byte(info, &cword, *src++);
  355. cnt--;
  356. cp++;
  357. }
  358. for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
  359. flash_add_byte(info, &cword, (*(uchar *)cp));
  360. if((rc = flash_write_cfiword(info, wp, cword)) != 0)
  361. return rc;
  362. wp = cp;
  363. }
  364. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  365. while(cnt >= info->portwidth) {
  366. i = info->buffer_size > cnt? cnt: info->buffer_size;
  367. if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
  368. return rc;
  369. wp += i;
  370. src += i;
  371. cnt -=i;
  372. }
  373. #else
  374. /* handle the aligned part */
  375. while(cnt >= info->portwidth) {
  376. cword.l = 0;
  377. for(i = 0; i < info->portwidth; i++) {
  378. flash_add_byte(info, &cword, *src++);
  379. }
  380. if((rc = flash_write_cfiword(info, wp, cword)) != 0)
  381. return rc;
  382. wp += info->portwidth;
  383. cnt -= info->portwidth;
  384. }
  385. #endif /* CFG_FLASH_USE_BUFFER_WRITE */
  386. if (cnt == 0) {
  387. return (0);
  388. }
  389. /*
  390. * handle unaligned tail bytes
  391. */
  392. cword.l = 0;
  393. for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
  394. flash_add_byte(info, &cword, *src++);
  395. --cnt;
  396. }
  397. for (; i<info->portwidth; ++i, ++cp) {
  398. flash_add_byte(info, & cword, (*(uchar *)cp));
  399. }
  400. return flash_write_cfiword(info, wp, cword);
  401. }
  402. /*-----------------------------------------------------------------------
  403. */
  404. #ifdef CFG_FLASH_PROTECTION
  405. int flash_real_protect(flash_info_t *info, long sector, int prot)
  406. {
  407. int retcode = 0;
  408. flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  409. flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
  410. if(prot)
  411. flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
  412. else
  413. flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
  414. if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
  415. prot?"protect":"unprotect")) == 0) {
  416. info->protect[sector] = prot;
  417. /* Intel's unprotect unprotects all locking */
  418. if(prot == 0) {
  419. flash_sect_t i;
  420. for(i = 0 ; i<info->sector_count; i++) {
  421. if(info->protect[i])
  422. flash_real_protect(info, i, 1);
  423. }
  424. }
  425. }
  426. return retcode;
  427. }
  428. /*-----------------------------------------------------------------------
  429. * flash_read_user_serial - read the OneTimeProgramming cells
  430. */
  431. void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len)
  432. {
  433. uchar * src;
  434. uchar * dst;
  435. dst = buffer;
  436. src = flash_make_addr(info, 0, FLASH_OFFSET_USER_PROTECTION);
  437. flash_write_cmd(info,0, 0, FLASH_CMD_READ_ID);
  438. memcpy(dst,src + offset,len);
  439. flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
  440. }
  441. /*
  442. * flash_read_factory_serial - read the device Id from the protection area
  443. */
  444. void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len)
  445. {
  446. uchar * src;
  447. src = flash_make_addr(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
  448. flash_write_cmd(info,0, 0, FLASH_CMD_READ_ID);
  449. memcpy(buffer,src + offset,len);
  450. flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
  451. }
  452. #endif /* CFG_FLASH_PROTECTION */
  453. static int flash_poll_status(flash_info_t * info, flash_sect_t sect)
  454. {
  455. int retval;
  456. switch(info->vendor) {
  457. case CFI_CMDSET_INTEL_STANDARD:
  458. case CFI_CMDSET_INTEL_EXTENDED:
  459. retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE);
  460. break;
  461. case CFI_CMDSET_AMD_STANDARD:
  462. case CFI_CMDSET_AMD_EXTENDED:
  463. retval = flash_toggle(info, sect, 0, AMD_STATUS_TOGGLE);
  464. break;
  465. default:
  466. retval = 0;
  467. }
  468. return retval;
  469. }
  470. /*-----------------------------------------------------------------------
  471. * wait for XSR.7 to be set. Time out with an error if it does not.
  472. * This routine does not set the flash to read-array mode.
  473. */
  474. static int flash_status_check(flash_info_t * info, flash_sect_t sector, ulong tout, char * prompt)
  475. {
  476. ulong start;
  477. /* Wait for command completion */
  478. start = get_timer (0);
  479. while (flash_poll_status(info, sector)) {
  480. if (get_timer(start) > info->erase_blk_tout) {
  481. printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
  482. flash_write_cmd(info, sector, 0, info->cmd_reset);
  483. return ERR_TIMOUT;
  484. }
  485. }
  486. return ERR_OK;
  487. }
  488. /*-----------------------------------------------------------------------
  489. * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
  490. * This routine sets the flash to read-array mode.
  491. */
  492. static int flash_full_status_check(flash_info_t * info, flash_sect_t sector, ulong tout, char * prompt)
  493. {
  494. int retcode;
  495. retcode = flash_status_check(info, sector, tout, prompt);
  496. switch(info->vendor) {
  497. case CFI_CMDSET_INTEL_EXTENDED:
  498. case CFI_CMDSET_INTEL_STANDARD:
  499. if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
  500. retcode = ERR_INVAL;
  501. printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
  502. if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
  503. printf("Command Sequence Error.\n");
  504. } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
  505. printf("Block Erase Error.\n");
  506. retcode = ERR_NOT_ERASED;
  507. } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
  508. printf("Locking Error\n");
  509. }
  510. if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
  511. printf("Block locked.\n");
  512. retcode = ERR_PROTECTED;
  513. }
  514. if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
  515. printf("Vpp Low Error.\n");
  516. }
  517. flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
  518. break;
  519. default:
  520. break;
  521. }
  522. return retcode;
  523. }
  524. /*-----------------------------------------------------------------------
  525. */
  526. static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
  527. {
  528. switch(info->portwidth) {
  529. case FLASH_CFI_8BIT:
  530. cword->c = c;
  531. break;
  532. case FLASH_CFI_16BIT:
  533. cword->w = (cword->w << 8) | c;
  534. break;
  535. case FLASH_CFI_32BIT:
  536. cword->l = (cword->l << 8) | c;
  537. break;
  538. case FLASH_CFI_64BIT:
  539. cword->ll = (cword->ll << 8) | c;
  540. break;
  541. }
  542. }
  543. /*-----------------------------------------------------------------------
  544. * make a proper sized command based on the port and chip widths
  545. */
  546. static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
  547. {
  548. int i;
  549. uchar *cp = (uchar *)cmdbuf;
  550. for(i=0; i< info->portwidth; i++)
  551. *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
  552. }
  553. /*
  554. * Write a proper sized command to the correct address
  555. */
  556. static void flash_write_cmd(flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  557. {
  558. volatile cfiptr_t addr;
  559. cfiword_t cword;
  560. addr.cp = flash_make_addr(info, sect, offset);
  561. flash_make_cmd(info, cmd, &cword);
  562. switch(info->portwidth) {
  563. case FLASH_CFI_8BIT:
  564. debug("fwc addr %p cmd %x %x 8bit x %d bit\n",addr.cp, cmd, cword.c,
  565. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  566. *addr.cp = cword.c;
  567. break;
  568. case FLASH_CFI_16BIT:
  569. debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n",addr.wp, cmd, cword.w,
  570. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  571. *addr.wp = cword.w;
  572. break;
  573. case FLASH_CFI_32BIT:
  574. debug("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n",addr.lp, cmd, cword.l,
  575. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  576. *addr.lp = cword.l;
  577. break;
  578. case FLASH_CFI_64BIT:
  579. #ifdef DEBUG
  580. {
  581. char str[20];
  582. print_longlong(str, cword.ll);
  583. printf("fwc addr %p cmd %x %s 64 bit x %d bit\n",addr.llp, cmd, str,
  584. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  585. }
  586. #endif
  587. *addr.llp = cword.ll;
  588. break;
  589. }
  590. }
  591. static void flash_unlock_seq(flash_info_t *info)
  592. {
  593. flash_write_cmd(info, 0, 0x555, 0xAA);
  594. flash_write_cmd(info, 0, 0x2AA, 0x55);
  595. }
  596. /*-----------------------------------------------------------------------
  597. */
  598. static int flash_isequal(flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  599. {
  600. cfiptr_t cptr;
  601. cfiword_t cword;
  602. int retval;
  603. cptr.cp = flash_make_addr(info, sect, offset);
  604. flash_make_cmd(info, cmd, &cword);
  605. debug("is= cmd %x(%c) addr %p ", cmd,cmd, cptr.cp);
  606. switch(info->portwidth) {
  607. case FLASH_CFI_8BIT:
  608. debug("is= %x %x\n", cptr.cp[0], cword.c);
  609. retval = (cptr.cp[0] == cword.c);
  610. break;
  611. case FLASH_CFI_16BIT:
  612. debug("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
  613. retval = (cptr.wp[0] == cword.w);
  614. break;
  615. case FLASH_CFI_32BIT:
  616. debug("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
  617. retval = (cptr.lp[0] == cword.l);
  618. break;
  619. case FLASH_CFI_64BIT:
  620. #ifdef DEBUG
  621. {
  622. char str1[20];
  623. char str2[20];
  624. print_longlong(str1, cptr.llp[0]);
  625. print_longlong(str2, cword.ll);
  626. printf("is= %s %s\n", str1, str2);
  627. }
  628. #endif
  629. retval = (cptr.llp[0] == cword.ll);
  630. break;
  631. default:
  632. retval = 0;
  633. break;
  634. }
  635. return retval;
  636. }
  637. /*-----------------------------------------------------------------------
  638. */
  639. static int flash_isset(flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  640. {
  641. cfiptr_t cptr;
  642. cfiword_t cword;
  643. int retval;
  644. cptr.cp = flash_make_addr(info, sect, offset);
  645. flash_make_cmd(info, cmd, &cword);
  646. switch(info->portwidth) {
  647. case FLASH_CFI_8BIT:
  648. retval = ((cptr.cp[0] & cword.c) == cword.c);
  649. break;
  650. case FLASH_CFI_16BIT:
  651. retval = ((cptr.wp[0] & cword.w) == cword.w);
  652. break;
  653. case FLASH_CFI_32BIT:
  654. retval = ((cptr.lp[0] & cword.l) == cword.l);
  655. break;
  656. case FLASH_CFI_64BIT:
  657. retval = ((cptr.llp[0] & cword.ll) == cword.ll);
  658. default:
  659. retval = 0;
  660. break;
  661. }
  662. return retval;
  663. }
  664. /*-----------------------------------------------------------------------
  665. */
  666. static int flash_toggle(flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
  667. {
  668. cfiptr_t cptr;
  669. cfiword_t cword;
  670. int retval;
  671. cptr.cp = flash_make_addr(info, sect, offset);
  672. flash_make_cmd(info, cmd, &cword);
  673. switch(info->portwidth) {
  674. case FLASH_CFI_8BIT:
  675. retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
  676. break;
  677. case FLASH_CFI_16BIT:
  678. retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
  679. break;
  680. case FLASH_CFI_32BIT:
  681. retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
  682. break;
  683. case FLASH_CFI_64BIT:
  684. retval = ((cptr.llp[0] & cword.ll) != (cptr.llp[0] & cword.ll));
  685. break;
  686. default:
  687. retval = 0;
  688. break;
  689. }
  690. return retval;
  691. }
  692. /*-----------------------------------------------------------------------
  693. * detect if flash is compatible with the Common Flash Interface (CFI)
  694. * http://www.jedec.org/download/search/jesd68.pdf
  695. *
  696. */
  697. static int flash_detect_cfi(flash_info_t * info)
  698. {
  699. puts("flash detect cfi\n");
  700. for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_64BIT;
  701. info->portwidth <<= 1) {
  702. /* for(info->chipwidth = info->portwidth;
  703. info->chipwidth > 0;
  704. info->chipwidth >>= 1) { */
  705. for(info->chipwidth =FLASH_CFI_BY8;
  706. info->chipwidth <= info->portwidth;
  707. info->chipwidth <<= 1) {
  708. flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
  709. flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
  710. if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
  711. flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
  712. flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
  713. debug("found port %d chip %d ", info->portwidth, info->chipwidth);
  714. debug("port %d bits chip %d bits\n", info->portwidth << CFI_FLASH_SHIFT_WIDTH,
  715. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  716. return 1;
  717. }
  718. }
  719. }
  720. puts("not found\n");
  721. return 0;
  722. }
  723. /*
  724. * The following code cannot be run from FLASH!
  725. *
  726. */
  727. static ulong flash_get_size (ulong base, int banknum)
  728. {
  729. flash_info_t * info = &flash_info[banknum];
  730. int i, j;
  731. flash_sect_t sect_cnt;
  732. unsigned long sector;
  733. unsigned long tmp;
  734. int size_ratio;
  735. uchar num_erase_regions;
  736. int erase_region_size;
  737. int erase_region_count;
  738. info->start[0] = base;
  739. if(flash_detect_cfi(info)){
  740. info->vendor = flash_read_ushort(info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
  741. switch(info->vendor) {
  742. case CFI_CMDSET_INTEL_STANDARD:
  743. case CFI_CMDSET_INTEL_EXTENDED:
  744. default:
  745. info->cmd_reset = FLASH_CMD_RESET;
  746. break;
  747. case CFI_CMDSET_AMD_STANDARD:
  748. case CFI_CMDSET_AMD_EXTENDED:
  749. info->cmd_reset = AMD_CMD_RESET;
  750. break;
  751. }
  752. debug("manufacturer is %d\n", info->vendor);
  753. size_ratio = info->portwidth / info->chipwidth;
  754. num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
  755. debug("size_ration %d port %d bits chip %d bits\n", size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
  756. info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
  757. debug("found %d erase regions\n", num_erase_regions);
  758. sect_cnt = 0;
  759. sector = base;
  760. for(i = 0 ; i < num_erase_regions; i++) {
  761. if(i > NUM_ERASE_REGIONS) {
  762. printf("%d erase regions found, only %d used\n",
  763. num_erase_regions, NUM_ERASE_REGIONS);
  764. break;
  765. }
  766. tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS + i*4);
  767. erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
  768. tmp >>= 16;
  769. erase_region_count = (tmp & 0xffff) +1;
  770. for(j = 0; j< erase_region_count; j++) {
  771. info->start[sect_cnt] = sector;
  772. sector += (erase_region_size * size_ratio);
  773. info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
  774. sect_cnt++;
  775. }
  776. }
  777. info->sector_count = sect_cnt;
  778. /* multiply the size by the number of chips */
  779. info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
  780. info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
  781. tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
  782. info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
  783. tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
  784. info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
  785. tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
  786. info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
  787. info->flash_id = FLASH_MAN_CFI;
  788. }
  789. flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
  790. return(info->size);
  791. }
  792. /*-----------------------------------------------------------------------
  793. */
  794. static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
  795. {
  796. cfiptr_t ctladdr;
  797. cfiptr_t cptr;
  798. int flag;
  799. ctladdr.cp = flash_make_addr(info, 0, 0);
  800. cptr.cp = (uchar *)dest;
  801. /* Check if Flash is (sufficiently) erased */
  802. switch(info->portwidth) {
  803. case FLASH_CFI_8BIT:
  804. flag = ((cptr.cp[0] & cword.c) == cword.c);
  805. break;
  806. case FLASH_CFI_16BIT:
  807. flag = ((cptr.wp[0] & cword.w) == cword.w);
  808. break;
  809. case FLASH_CFI_32BIT:
  810. flag = ((cptr.lp[0] & cword.l) == cword.l);
  811. break;
  812. case FLASH_CFI_64BIT:
  813. flag = ((cptr.lp[0] & cword.ll) == cword.ll);
  814. break;
  815. default:
  816. return 2;
  817. }
  818. if(!flag)
  819. return 2;
  820. /* Disable interrupts which might cause a timeout here */
  821. flag = disable_interrupts();
  822. switch(info->vendor) {
  823. case CFI_CMDSET_INTEL_EXTENDED:
  824. case CFI_CMDSET_INTEL_STANDARD:
  825. flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
  826. flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
  827. break;
  828. case CFI_CMDSET_AMD_EXTENDED:
  829. case CFI_CMDSET_AMD_STANDARD:
  830. flash_unlock_seq(info);
  831. flash_write_cmd(info, 0, 0x555, AMD_CMD_WRITE);
  832. break;
  833. }
  834. switch(info->portwidth) {
  835. case FLASH_CFI_8BIT:
  836. cptr.cp[0] = cword.c;
  837. break;
  838. case FLASH_CFI_16BIT:
  839. cptr.wp[0] = cword.w;
  840. break;
  841. case FLASH_CFI_32BIT:
  842. cptr.lp[0] = cword.l;
  843. break;
  844. case FLASH_CFI_64BIT:
  845. cptr.llp[0] = cword.ll;
  846. break;
  847. }
  848. /* re-enable interrupts if necessary */
  849. if(flag)
  850. enable_interrupts();
  851. return flash_full_status_check(info, 0, info->write_tout, "write");
  852. }
  853. #ifdef CFG_FLASH_USE_BUFFER_WRITE
  854. /* loop through the sectors from the highest address
  855. * when the passed address is greater or equal to the sector address
  856. * we have a match
  857. */
  858. static flash_sect_t find_sector(flash_info_t *info, ulong addr)
  859. {
  860. flash_sect_t sector;
  861. for(sector = info->sector_count - 1; sector >= 0; sector--) {
  862. if(addr >= info->start[sector])
  863. break;
  864. }
  865. return sector;
  866. }
  867. static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
  868. {
  869. flash_sect_t sector;
  870. int cnt;
  871. int retcode;
  872. volatile cfiptr_t src;
  873. volatile cfiptr_t dst;
  874. src.cp = cp;
  875. dst.cp = (uchar *)dest;
  876. sector = find_sector(info, dest);
  877. flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  878. flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
  879. if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
  880. "write to buffer")) == ERR_OK) {
  881. switch(info->portwidth) {
  882. case FLASH_CFI_8BIT:
  883. cnt = len;
  884. break;
  885. case FLASH_CFI_16BIT:
  886. cnt = len >> 1;
  887. break;
  888. case FLASH_CFI_32BIT:
  889. cnt = len >> 2;
  890. break;
  891. case FLASH_CFI_64BIT:
  892. cnt = len >> 3;
  893. break;
  894. default:
  895. return ERR_INVAL;
  896. break;
  897. }
  898. flash_write_cmd(info, sector, 0, (uchar)cnt-1);
  899. while(cnt-- > 0) {
  900. switch(info->portwidth) {
  901. case FLASH_CFI_8BIT:
  902. *dst.cp++ = *src.cp++;
  903. break;
  904. case FLASH_CFI_16BIT:
  905. *dst.wp++ = *src.wp++;
  906. break;
  907. case FLASH_CFI_32BIT:
  908. *dst.lp++ = *src.lp++;
  909. break;
  910. case FLASH_CFI_64BIT:
  911. *dst.llp++ = *src.llp++;
  912. break;
  913. default:
  914. return ERR_INVAL;
  915. break;
  916. }
  917. }
  918. flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
  919. retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
  920. "buffer write");
  921. }
  922. flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
  923. return retcode;
  924. }
  925. #endif /* CFG_USE_FLASH_BUFFER_WRITE */
  926. #endif /* CFG_FLASH_CFI */