mx25pdk.c 4.2 KB

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  1. /*
  2. * (C) Copyright 2011 Freescale Semiconductor, Inc.
  3. *
  4. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. */
  19. #include <common.h>
  20. #include <asm/io.h>
  21. #include <asm/gpio.h>
  22. #include <asm/arch/imx-regs.h>
  23. #include <asm/arch/imx25-pinmux.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/arch/clock.h>
  26. #include <mmc.h>
  27. #include <fsl_esdhc.h>
  28. #include <i2c.h>
  29. #include <power/pmic.h>
  30. #include <fsl_pmic.h>
  31. #include <mc34704.h>
  32. #define FEC_RESET_B IMX_GPIO_NR(2, 3)
  33. #define FEC_ENABLE_B IMX_GPIO_NR(4, 8)
  34. #define CARD_DETECT IMX_GPIO_NR(2, 1)
  35. DECLARE_GLOBAL_DATA_PTR;
  36. #ifdef CONFIG_FSL_ESDHC
  37. struct fsl_esdhc_cfg esdhc_cfg[1] = {
  38. {IMX_MMC_SDHC1_BASE},
  39. };
  40. #endif
  41. static void mx25pdk_fec_init(void)
  42. {
  43. struct iomuxc_mux_ctl *muxctl;
  44. struct iomuxc_pad_ctl *padctl;
  45. u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
  46. u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
  47. /* FEC pin init is generic */
  48. mx25_fec_init_pins();
  49. muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
  50. padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
  51. /*
  52. * Set up FEC_RESET_B and FEC_ENABLE_B
  53. *
  54. * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
  55. * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
  56. */
  57. writel(gpio_mux_mode, &muxctl->pad_d12);
  58. writel(gpio_mux_mode, &muxctl->pad_a17);
  59. writel(0x0, &padctl->pad_d12);
  60. writel(0x0, &padctl->pad_a17);
  61. /* Assert RESET and ENABLE low */
  62. gpio_direction_output(FEC_RESET_B, 0);
  63. gpio_direction_output(FEC_ENABLE_B, 0);
  64. udelay(10);
  65. /* Deassert RESET and ENABLE */
  66. gpio_set_value(FEC_RESET_B, 1);
  67. gpio_set_value(FEC_ENABLE_B, 1);
  68. /* Setup I2C pins so that PMIC can turn on PHY supply */
  69. writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
  70. writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
  71. writel(0x1E8, &padctl->pad_i2c1_clk);
  72. writel(0x1E8, &padctl->pad_i2c1_dat);
  73. }
  74. int dram_init(void)
  75. {
  76. /* dram_init must store complete ramsize in gd->ram_size */
  77. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  78. PHYS_SDRAM_1_SIZE);
  79. return 0;
  80. }
  81. int board_early_init_f(void)
  82. {
  83. mx25_uart1_init_pins();
  84. return 0;
  85. }
  86. int board_init(void)
  87. {
  88. /* address of boot parameters */
  89. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  90. return 0;
  91. }
  92. int board_late_init(void)
  93. {
  94. struct pmic *p;
  95. int ret;
  96. mx25pdk_fec_init();
  97. ret = pmic_init(I2C_PMIC);
  98. if (ret)
  99. return ret;
  100. p = pmic_get("FSL_PMIC");
  101. if (!p)
  102. return -ENODEV;
  103. /* Turn on Ethernet PHY supply */
  104. pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
  105. return 0;
  106. }
  107. #ifdef CONFIG_FSL_ESDHC
  108. int board_mmc_getcd(struct mmc *mmc)
  109. {
  110. struct iomuxc_mux_ctl *muxctl;
  111. struct iomuxc_pad_ctl *padctl;
  112. u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
  113. /*
  114. * Set up the Card Detect pin.
  115. *
  116. * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15
  117. *
  118. */
  119. muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
  120. padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
  121. writel(gpio_mux_mode, &muxctl->pad_a15);
  122. writel(0x0, &padctl->pad_a15);
  123. gpio_direction_input(CARD_DETECT);
  124. return !gpio_get_value(CARD_DETECT);
  125. }
  126. int board_mmc_init(bd_t *bis)
  127. {
  128. struct iomuxc_mux_ctl *muxctl;
  129. u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
  130. muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
  131. writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd);
  132. writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk);
  133. writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0);
  134. writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1);
  135. writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2);
  136. writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3);
  137. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  138. return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
  139. }
  140. #endif
  141. int checkboard(void)
  142. {
  143. puts("Board: MX25PDK\n");
  144. return 0;
  145. }