tegra30-common.h 3.1 KB

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  1. /*
  2. * (C) Copyright 2010-2012
  3. * NVIDIA Corporation <www.nvidia.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef _TEGRA30_COMMON_H_
  24. #define _TEGRA30_COMMON_H_
  25. #include "tegra-common.h"
  26. /*
  27. * NS16550 Configuration
  28. */
  29. #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
  30. /*
  31. * High Level Configuration Options
  32. */
  33. #define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
  34. /* Environment information, boards can override if required */
  35. #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
  36. /*
  37. * Miscellaneous configurable options
  38. */
  39. #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
  40. #define CONFIG_STACKBASE 0x82800000 /* 40MB */
  41. /*-----------------------------------------------------------------------
  42. * Physical Memory Map
  43. */
  44. #define CONFIG_SYS_TEXT_BASE 0x8010E000
  45. /*
  46. * Memory layout for where various images get loaded by boot scripts:
  47. *
  48. * scriptaddr can be pretty much anywhere that doesn't conflict with something
  49. * else. Put it above BOOTMAPSZ to eliminate conflicts.
  50. *
  51. * kernel_addr_r must be within the first 128M of RAM in order for the
  52. * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  53. * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  54. * should not overlap that area, or the kernel will have to copy itself
  55. * somewhere else before decompression. Similarly, the address of any other
  56. * data passed to the kernel shouldn't overlap the start of RAM. Pushing
  57. * this up to 16M allows for a sizable kernel to be decompressed below the
  58. * compressed load address.
  59. *
  60. * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  61. * the compressed kernel to be up to 16M too.
  62. *
  63. * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  64. * for the FDT/DTB to be up to 1M, which is hopefully plenty.
  65. */
  66. #define MEM_LAYOUT_ENV_SETTINGS \
  67. "scriptaddr=0x90000000\0" \
  68. "kernel_addr_r=0x81000000\0" \
  69. "fdt_addr_r=0x82000000\0" \
  70. "ramdisk_addr_r=0x82100000\0"
  71. /* Defines for SPL */
  72. #define CONFIG_SPL_TEXT_BASE 0x80108000
  73. #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
  74. #define CONFIG_SPL_STACK 0x800ffffc
  75. #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
  76. /* Total I2C ports on Tegra30 */
  77. #define TEGRA_I2C_NUM_CONTROLLERS 5
  78. /* Misc utility code */
  79. #define CONFIG_BOUNCE_BUFFER
  80. #endif /* _TEGRA30_COMMON_H_ */