smiLynxEM.c 34 KB

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  1. /*
  2. * (C) Copyright 1997-2002 ELTEC Elektronik AG
  3. * Frank Gottschling <fgottschling@eltec.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * smiLynxEM.c
  25. *
  26. * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
  27. *
  28. * modification history
  29. * --------------------
  30. * 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
  31. *
  32. */
  33. #include <common.h>
  34. #if defined(CONFIG_VIDEO_SMI_LYNXEM)
  35. #include <pci.h>
  36. #include <video_fb.h>
  37. /*
  38. * Export Graphic Device
  39. */
  40. GraphicDevice smi;
  41. /*
  42. * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external
  43. */
  44. #define VIDEO_MEM_SIZE 0x400000
  45. /*
  46. * Supported video modes for SMI Lynx E/EM/EM+
  47. */
  48. #define VIDEO_MODES 7
  49. #define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */
  50. /* VGA2:60/120Hz (pitch=1600) */
  51. /* SMI810:VGA1:75Hz (pitch=1600) */
  52. /* VGA2:75Hz (pitch=1600) */
  53. #define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */
  54. #define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */
  55. #define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */
  56. #define SINGLE_1280_1024 4 /* VGA1:75Hz (pitch=1280) */
  57. #define TV_MODE_CCIR 5 /* VGA1:50Hz (h=720;v=576;pitch=720) */
  58. #define TV_MODE_EIA 6 /* VGA1:60Hz (h=720;v=484;pitch=720) */
  59. /*
  60. * ISA mapped regs
  61. */
  62. #define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */
  63. #define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */
  64. #define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */
  65. #define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */
  66. #define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */
  67. #define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */
  68. #define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */
  69. #define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */
  70. #define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */
  71. #define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */
  72. #define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/
  73. /*
  74. * Video processor control
  75. */
  76. typedef struct {
  77. unsigned int control;
  78. unsigned int colorKey;
  79. unsigned int colorKeyMask;
  80. unsigned int start;
  81. unsigned short offset;
  82. unsigned short width;
  83. unsigned int fifoPrio;
  84. unsigned int fifoERL;
  85. unsigned int YUVtoRGB;
  86. } SmiVideoProc;
  87. /*
  88. * Video window control
  89. */
  90. typedef struct {
  91. unsigned short top;
  92. unsigned short left;
  93. unsigned short bottom;
  94. unsigned short right;
  95. unsigned int srcStart;
  96. unsigned short width;
  97. unsigned short offset;
  98. unsigned char hStretch;
  99. unsigned char vStretch;
  100. } SmiVideoWin;
  101. /*
  102. * Capture port control
  103. */
  104. typedef struct {
  105. unsigned int control;
  106. unsigned short topClip;
  107. unsigned short leftClip;
  108. unsigned short srcHeight;
  109. unsigned short srcWidth;
  110. unsigned int srcBufStart1;
  111. unsigned int srcBufStart2;
  112. unsigned short srcOffset;
  113. unsigned short fifoControl;
  114. } SmiCapturePort;
  115. /*
  116. * Register values for common video modes
  117. */
  118. static char SMI_SCR[22] = {
  119. /* all modes */
  120. 0x10, 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x14, 0x00, 0x15, 0x90,
  121. 0x16, 0x10, 0x17, 0x2c, 0x18, 0xb1, 0x19, 0x20, 0x1a, 0x01
  122. };
  123. static char SMI_EXT_CRT[VIDEO_MODES][24] = {
  124. { /* DUAL_800_600_8 */
  125. 0x30, 0x00, 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
  126. 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00
  127. },
  128. { /* DUAL_1024_768_8 */
  129. 0x30, 0x00, 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
  130. 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00
  131. },
  132. { /* SINGLE_800_600_8 */
  133. 0x30, 0x00, 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
  134. 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00
  135. },
  136. { /* SINGLE_1024_768_8 */
  137. 0x30, 0x00, 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
  138. 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00
  139. },
  140. { /* SINGLE_1280_1024_8 */
  141. 0x30, 0x09, 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
  142. 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00
  143. },
  144. { /* TV_MODE_CCIR */
  145. 0x30, 0x80, 0x31, 0x2b, 0x32, 0x06, 0x33, 0x01, 0x34, 0x26, 0x35, 0x88,
  146. 0x36, 0x02, 0x38, 0x11, 0x39, 0x11, 0x3a, 0x20, 0x3e, 0xa3, 0x3f, 0x00
  147. },
  148. { /* TV_MODE_EIA */
  149. 0x30, 0x80, 0x31, 0x2b, 0x32, 0x06, 0x33, 0x00, 0x34, 0xf8, 0x35, 0x88,
  150. 0x36, 0x02, 0x38, 0x11, 0x39, 0x11, 0x3a, 0x20, 0x3e, 0xa3, 0x3f, 0x00
  151. },
  152. };
  153. static char SMI_CRTCR[VIDEO_MODES][50] = {
  154. { /* DUAL_800_600_8 */
  155. 0x00, 0x7f, 0x01, 0x63, 0x02, 0x63, 0x03, 0x00, 0x04, 0x68, 0x05, 0x12,
  156. 0x06, 0x6f, 0x07, 0xf0, 0x08, 0x00, 0x09, 0x60, 0x0a, 0x00, 0x0b, 0x00,
  157. 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x10, 0x59, 0x11, 0x2c,
  158. 0x12, 0x57, 0x13, 0x64, 0x14, 0x40, 0x15, 0x57, 0x16, 0x00, 0x17, 0xe3,
  159. 0x18, 0xff
  160. },
  161. { /* DUAL_1024_768_8 */
  162. 0x00, 0x9f, 0x01, 0x7f, 0x02, 0x7f, 0x03, 0x00, 0x04, 0x82, 0x05, 0x0e,
  163. 0x06, 0x1e, 0x07, 0xf5, 0x08, 0x00, 0x09, 0x60, 0x0a, 0x00, 0x0b, 0x00,
  164. 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x10, 0x01, 0x11, 0x24,
  165. 0x12, 0xff, 0x13, 0x80, 0x14, 0x40, 0x15, 0xff, 0x16, 0x00, 0x17, 0xe3,
  166. 0x18, 0xff
  167. },
  168. { /* SINGLE_800_600_8 */
  169. 0x00, 0x7f, 0x01, 0x63, 0x02, 0x63, 0x03, 0x00, 0x04, 0x68, 0x05, 0x12,
  170. 0x06, 0x6f, 0x07, 0xf0, 0x08, 0x00, 0x09, 0x60, 0x0a, 0x00, 0x0b, 0x00,
  171. 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x10, 0x59, 0x11, 0x2c,
  172. 0x12, 0x57, 0x13, 0x32, 0x14, 0x40, 0x15, 0x57, 0x16, 0x00, 0x17, 0xe3,
  173. 0x18, 0xff
  174. },
  175. { /* SINGLE_1024_768_8 */
  176. 0x00, 0x9f, 0x01, 0x7f, 0x02, 0x7f, 0x03, 0x00, 0x04, 0x82, 0x05, 0x0e,
  177. 0x06, 0x1e, 0x07, 0xf5, 0x08, 0x00, 0x09, 0x60, 0x0a, 0x00, 0x0b, 0x00,
  178. 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x10, 0x01, 0x11, 0x24,
  179. 0x12, 0xff, 0x13, 0x40, 0x14, 0x40, 0x15, 0xff, 0x16, 0x00, 0x17, 0xe3,
  180. 0x18, 0xff
  181. },
  182. { /* SINGLE_1280_1024_8 */
  183. 0x00, 0xce, 0x01, 0x9f, 0x02, 0x9f, 0x03, 0x00, 0x04, 0xa2, 0x05, 0x12,
  184. 0x06, 0x2a, 0x07, 0x5a, 0x08, 0x00, 0x09, 0x60, 0x0a, 0x00, 0x0b, 0x00,
  185. 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x10, 0x01, 0x11, 0x23,
  186. 0x12, 0xff, 0x13, 0x50, 0x14, 0x40, 0x15, 0xff, 0x16, 0x00, 0x17, 0xe3,
  187. 0x18, 0xff
  188. },
  189. { /* TV_MODE_CCIR */
  190. 0x00, 0x00, 0x01, 0x59, 0x02, 0x63, 0x03, 0x00, 0x04, 0x69, 0x05, 0x10,
  191. 0x06, 0x72, 0x07, 0xf0, 0x08, 0x00, 0x09, 0x60, 0x0a, 0x00, 0x0b, 0x00,
  192. 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x10, 0x58, 0x11, 0x2c,
  193. 0x12, 0x57, 0x13, 0x2d, 0x14, 0x40, 0x15, 0x57, 0x16, 0x00, 0x17, 0xe3,
  194. 0x18, 0xff
  195. },
  196. { /* TV_MODE_EIA */
  197. 0x00, 0x00, 0x01, 0x59, 0x02, 0x63, 0x03, 0x00, 0x04, 0x69, 0x05, 0x10,
  198. 0x06, 0x72, 0x07, 0xf0, 0x08, 0x00, 0x09, 0x60, 0x0a, 0x00, 0x0b, 0x00,
  199. 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x10, 0x58, 0x11, 0x2c,
  200. 0x12, 0x57, 0x13, 0x2d, 0x14, 0x40, 0x15, 0x57, 0x16, 0x00, 0x17, 0xe3,
  201. 0x18, 0xff
  202. },
  203. };
  204. static char SMI_SEQR[10] = {
  205. 0x00, 0x03, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e
  206. };
  207. static char SMI_PCR[VIDEO_MODES][8] = {
  208. { /* DUAL_800_600_8 */
  209. 0x20, 0x04, 0x21, 0x20, 0x22, 0x00, 0x23, 0x00
  210. },
  211. { /* DUAL_1024_768_8 */
  212. 0x20, 0x04, 0x21, 0x20, 0x22, 0x00, 0x23, 0x00
  213. },
  214. { /* SINGLE_800_600_8 */
  215. 0x20, 0x04, 0x21, 0x30, 0x22, 0x02, 0x23, 0x00
  216. },
  217. { /* SINGLE_1024_768_8 */
  218. 0x20, 0x04, 0x21, 0x30, 0x22, 0x02, 0x23, 0x00
  219. },
  220. { /* SINGLE_1280_1024_8 */
  221. 0x20, 0x04, 0x21, 0x30, 0x22, 0x02, 0x23, 0x00
  222. },
  223. { /* TV_MODE_CCIR */
  224. 0x20, 0x04, 0x21, 0x30, 0x22, 0x02, 0x23, 0x00
  225. },
  226. { /* TV_MODE_EIA */
  227. 0x20, 0x04, 0x21, 0x30, 0x22, 0x02, 0x23, 0x00
  228. },
  229. };
  230. static char SMI_MCR[VIDEO_MODES][6] = {
  231. { /* DUAL_800_600_8 */
  232. 0x60, 0x01, 0x61, 0x00, 0x62, 0x7a
  233. },
  234. { /* DUAL_1024_768_8 */
  235. 0x60, 0x01, 0x61, 0x00, 0x62, 0x7a
  236. },
  237. { /* SINGLE_800_600_8 */
  238. 0x60, 0x00, 0x61, 0x00, 0x62, 0x34
  239. },
  240. { /* SINGLE_1024_768_8 */
  241. 0x60, 0x00, 0x61, 0x00, 0x62, 0xfe
  242. },
  243. { /* SINGLE_1280_1024_8 */
  244. 0x60, 0x00, 0x61, 0x00, 0x62, 0xfe
  245. },
  246. { /* TV_MODE_CCIR */
  247. 0x60, 0x00, 0x61, 0x00, 0x62, 0x34
  248. },
  249. { /* TV_MODE_EIA */
  250. 0x60, 0x00, 0x61, 0x00, 0x62, 0x34
  251. },
  252. };
  253. static char SMI_CCR[VIDEO_MODES][18] = {
  254. { /* DUAL_800_600_8 */
  255. 0x65, 0x34, 0x68, 0x50, 0x69, 0x05, 0x6a, 0x53, 0x6b, 0x15, 0x6c, 0x15,
  256. 0x6d, 0x06, 0x6e, 0x3d, 0x6f, 0x12
  257. },
  258. { /* DUAL_1024_768_8 */
  259. 0x65, 0x00, 0x68, 0x50, 0x69, 0x06, 0x6a, 0x53, 0x6b, 0x15, 0x6c, 0x0b,
  260. 0x6d, 0x02, 0x6e, 0x0b, 0x6f, 0x02
  261. },
  262. { /* SINGLE_800_600_8 */
  263. 0x65, 0x34, 0x68, 0x40, 0x69, 0x03, 0x6a, 0x53, 0x6b, 0x15, 0x6c, 0x15,
  264. 0x6d, 0x06, 0x6e, 0x3d, 0x6f, 0x12
  265. },
  266. { /* SINGLE_1024_768_8 */
  267. 0x65, 0x00, 0x68, 0x50, 0x69, 0x03, 0x6a, 0x53, 0x6b, 0x15, 0x6c, 0x0b,
  268. 0x6d, 0x02, 0x6e, 0x0b, 0x6f, 0x02
  269. },
  270. { /* SINGLE_1280_1024_8 */
  271. 0x65, 0x00, 0x68, 0x50, 0x69, 0x03, 0x6a, 0x53, 0x6b, 0x15, 0x6c, 0xd9,
  272. 0x6d, 0x17, 0x6e, 0xd9, 0x6f, 0x17
  273. },
  274. { /* TV_MODE_CCIR */
  275. 0x65, 0x07, 0x68, 0xc0, 0x69, 0x81, 0x6a, 0x53, 0x6b, 0x15, 0x6c, 0x15,
  276. 0x6d, 0x06, 0x6e, 0x3d, 0x6f, 0x12
  277. },
  278. { /* TV_MODE_EIA */
  279. 0x65, 0x07, 0x68, 0xc0, 0x69, 0x81, 0x6a, 0x53, 0x6b, 0x15, 0x6c, 0x15,
  280. 0x6d, 0x06, 0x6e, 0x3d, 0x6f, 0x12
  281. },
  282. };
  283. static char SMI_SHVGA[VIDEO_MODES][24] = {
  284. { /* DUAL_800_600_8 */
  285. 0x40, 0x7f, 0x41, 0x63, 0x42, 0x00, 0x43, 0x68, 0x44, 0x12, 0x45, 0x6f,
  286. 0x46, 0x57, 0x47, 0x00, 0x48, 0x59, 0x49, 0x0c, 0x4a, 0xa0, 0x4b, 0x20,
  287. },
  288. { /* DUAL_1024_768_8 */
  289. 0x40, 0x9f, 0x41, 0x7f, 0x42, 0x00, 0x43, 0x82, 0x44, 0x0e, 0x45, 0x1e,
  290. 0x46, 0xff, 0x47, 0x00, 0x48, 0x00, 0x49, 0x03, 0x4a, 0xe5, 0x4b, 0x20,
  291. },
  292. { /* SINGLE_800_600_8 */
  293. 0x40, 0x7f, 0x41, 0x63, 0x42, 0x00, 0x43, 0x68, 0x44, 0x12, 0x45, 0x6f,
  294. 0x46, 0x57, 0x47, 0x00, 0x48, 0x59, 0x49, 0x0c, 0x4a, 0xa0, 0x4b, 0x20,
  295. },
  296. { /* SINGLE_1024_768_8 */
  297. 0x40, 0x9f, 0x41, 0x7f, 0x42, 0x00, 0x43, 0x82, 0x44, 0x0e, 0x45, 0x1e,
  298. 0x46, 0xff, 0x47, 0x00, 0x48, 0x01, 0x49, 0x04, 0x4a, 0xa5, 0x4b, 0x20,
  299. },
  300. { /* SINGLE_1280_1024_8 */
  301. 0x40, 0xce, 0x41, 0x9f, 0x42, 0x00, 0x43, 0xa2, 0x44, 0x12, 0x45, 0x2a,
  302. 0x46, 0xff, 0x47, 0x00, 0x48, 0x01, 0x49, 0x03, 0x4a, 0x4a, 0x4b, 0x20,
  303. },
  304. { /* TV_MODE_CCIR */
  305. 0x40, 0x6d, 0x41, 0x59, 0x42, 0x00, 0x43, 0x60, 0x44, 0x09, 0x45, 0x38,
  306. 0x46, 0x25, 0x47, 0x05, 0x48, 0x2a, 0x49, 0x00, 0x4a, 0x4d, 0x4b, 0x00,
  307. },
  308. { /* TV_MODE_EIA */
  309. 0x40, 0x6d, 0x41, 0x59, 0x42, 0x00, 0x43, 0x60, 0x44, 0x09, 0x45, 0x06,
  310. 0x46, 0xf7, 0x47, 0x05, 0x48, 0xfa, 0x49, 0x00, 0x4a, 0x41, 0x4b, 0x00,
  311. },
  312. };
  313. static char SMI_GPR[VIDEO_MODES][12] = {
  314. { /* DUAL_800_600_8 */
  315. 0x70, 0x00, 0x71, 0xa2, 0x72, 0x0f, 0x73, 0x30, 0x74, 0x40, 0x75, 0x00
  316. },
  317. { /* DUAL_1024_768_8 */
  318. 0x70, 0x00, 0x71, 0xa2, 0x72, 0x0f, 0x73, 0x30, 0x74, 0x40, 0x75, 0x00
  319. },
  320. { /* SINGLE_800_600_8 */
  321. 0x70, 0x00, 0x71, 0xa2, 0x72, 0x0f, 0x73, 0x30, 0x74, 0x40, 0x75, 0x00
  322. },
  323. { /* SINGLE_1024_768_8 */
  324. 0x70, 0x00, 0x71, 0xa2, 0x72, 0x0f, 0x73, 0x30, 0x74, 0x40, 0x75, 0x00
  325. },
  326. { /* SINGLE_1280_1024_8 */
  327. 0x70, 0x00, 0x71, 0xa2, 0x72, 0x0f, 0x73, 0x30, 0x74, 0x40, 0x75, 0x00
  328. },
  329. { /* TV_MODE_CCIR */
  330. 0x70, 0x82, 0x71, 0x8d, 0x72, 0x0c, 0x73, 0x32, 0x74, 0x09, 0x75, 0x28
  331. },
  332. { /* TV_MODE_EIA */
  333. 0x70, 0x82, 0x71, 0x8d, 0x72, 0x0c, 0x73, 0x32, 0x74, 0x09, 0x75, 0x28
  334. },
  335. };
  336. static char SMI_HCR[VIDEO_MODES][22] = {
  337. { /* DUAL_800_600_8 */
  338. 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
  339. 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00
  340. },
  341. { /* DUAL_1024_768_8 */
  342. 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
  343. 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00
  344. },
  345. { /* SINGLE_800_600_8 */
  346. 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
  347. 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00
  348. },
  349. { /* SINGLE_1024_768_8 */
  350. 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
  351. 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00
  352. },
  353. { /* SINGLE_1280_1024_8 */
  354. 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
  355. 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00
  356. },
  357. { /* TV_MODE_CCIR */
  358. 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
  359. 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00
  360. },
  361. { /* TV_MODE_EIA */
  362. 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
  363. 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00
  364. },
  365. };
  366. static char SMI_FPR[VIDEO_MODES][88] = {
  367. { /* DUAL_800_600_8 */
  368. 0x30, 0x36, 0x31, 0x83, 0x32, 0x38, 0x33, 0x00, 0x34, 0x40, 0x3e, 0x03,
  369. 0x3f, 0xff, 0x40, 0x64, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0xc8,
  370. 0x45, 0x02, 0x46, 0x00, 0x47, 0xfc, 0x48, 0x20, 0x49, 0x1c, 0x4a, 0x41,
  371. 0x4b, 0xa0, 0x4c, 0x00,
  372. 0x50, 0x04, 0x51, 0x48, 0x52, 0x83, 0x53, 0x63, 0x54, 0x67, 0x55, 0x71,
  373. 0x56, 0x57, 0x57, 0x59, 0x58, 0x03, 0x59, 0x00, 0x5a, 0x4a,
  374. 0xa1, 0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa8, 0x00, 0xa9, 0x00,
  375. 0xaa, 0xdf, 0xab, 0x7f, 0xac, 0x00, 0xad, 0x41, 0xae, 0x00, 0xaf, 0x00,
  376. 0xa0, 0x44
  377. },
  378. { /* DUAL_1024_768_8 */
  379. 0x30, 0x3a, 0x31, 0x83, 0x32, 0x38, 0x33, 0x00, 0x34, 0x40, 0x3e, 0x00,
  380. 0x3f, 0x00, 0x40, 0x80, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0x00,
  381. 0x45, 0x42, 0x46, 0x00, 0x47, 0xfc, 0x48, 0x20, 0x49, 0x1c, 0x4a, 0x41,
  382. 0x4b, 0xa0, 0x4c, 0x00,
  383. 0x50, 0x06, 0x51, 0x68, 0x52, 0xa7, 0x53, 0x7f, 0x54, 0x83, 0x55, 0x25,
  384. 0x56, 0xff, 0x57, 0x03, 0x58, 0x04, 0x59, 0x00, 0x5a, 0xc2,
  385. 0xa1, 0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa8, 0x00, 0xa9, 0x00,
  386. 0xaa, 0xdf, 0xab, 0x7f, 0xac, 0x00, 0xad, 0x41, 0xae, 0x00, 0xaf, 0x00,
  387. 0xa0, 0x44
  388. },
  389. { /* SINGLE_800_600_8 */
  390. 0x30, 0x36, 0x31, 0x82, 0x32, 0x38, 0x33, 0x00, 0x34, 0x40, 0x3e, 0x03,
  391. 0x3f, 0xff, 0x40, 0x64, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0xc8,
  392. 0x45, 0x02, 0x46, 0x00, 0x47, 0xfc, 0x48, 0x20, 0x49, 0x1c, 0x4a, 0x00,
  393. 0x4b, 0xa0, 0x4c, 0x00,
  394. 0x50, 0x04, 0x51, 0x48, 0x52, 0x83, 0x53, 0x63, 0x54, 0x67, 0x55, 0x71,
  395. 0x56, 0x57, 0x57, 0x59, 0x58, 0x03, 0x59, 0x00, 0x5a, 0x4a,
  396. 0xa1, 0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa8, 0x00, 0xa9, 0x00,
  397. 0xaa, 0xdf, 0xab, 0x7f, 0xac, 0x00, 0xad, 0x41, 0xae, 0x00, 0xaf, 0x00,
  398. 0xa0, 0x44
  399. },
  400. { /* SINGLE_1024_768_8 */
  401. 0x30, 0x3a, 0x31, 0x82, 0x32, 0x38, 0x33, 0x00, 0x34, 0x40, 0x3e, 0x00,
  402. 0x3f, 0x00, 0x40, 0x80, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0x00,
  403. 0x45, 0x42, 0x46, 0x00, 0x47, 0xfc, 0x48, 0x20, 0x49, 0x1c, 0x4a, 0x11,
  404. 0x4b, 0xa0, 0x4c, 0x00,
  405. 0x50, 0x06, 0x51, 0x68, 0x52, 0xa7, 0x53, 0x7f, 0x54, 0x83, 0x55, 0x24,
  406. 0x56, 0xff, 0x57, 0x03, 0x58, 0x04, 0x59, 0x00, 0x5a, 0xc2,
  407. 0xa1, 0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa8, 0x00, 0xa9, 0x00,
  408. 0xaa, 0xdf, 0xab, 0x7f, 0xac, 0x00, 0xad, 0x41, 0xae, 0x00, 0xaf, 0x00,
  409. 0xa0, 0x44
  410. },
  411. { /* SINGLE_1280_1024_8 */
  412. 0x30, 0x3e, 0x31, 0x82, 0x32, 0x38, 0x33, 0x00, 0x34, 0x40, 0x3e, 0x00,
  413. 0x3f, 0x00, 0x40, 0xa0, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0x00,
  414. 0x45, 0x42, 0x46, 0x00, 0x47, 0xfc, 0x48, 0x20, 0x49, 0x1c, 0x4a, 0x11,
  415. 0x4b, 0xa0, 0x4c, 0x00,
  416. 0x50, 0x08, 0x51, 0x88, 0x52, 0xd3, 0x53, 0x9f, 0x54, 0xa3, 0x55, 0x2a,
  417. 0x56, 0xff, 0x57, 0x04, 0x58, 0x00, 0x59, 0x00, 0x5a, 0x63,
  418. 0xa1, 0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa8, 0x00, 0xa9, 0x00,
  419. 0xaa, 0xdf, 0xab, 0x7f, 0xac, 0x00, 0xad, 0x41, 0xae, 0x00, 0xaf, 0x00,
  420. 0xa0, 0x44
  421. },
  422. { /* TV_MODE_CCIR */
  423. 0x30, 0x24, 0x31, 0x84, 0x32, 0x20, 0x33, 0x09, 0x34, 0xf0, 0x3e, 0x03,
  424. 0x3f, 0xff, 0x40, 0x64, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0xc8,
  425. 0x45, 0x02, 0x46, 0x00, 0x47, 0xfc, 0x48, 0x20, 0x49, 0x1c, 0x4a, 0x00,
  426. 0x4b, 0xa0, 0x4c, 0x00,
  427. 0x50, 0x04, 0x51, 0x48, 0x52, 0x83, 0x53, 0x63, 0x54, 0x68, 0x55, 0x73,
  428. 0x56, 0x57, 0x57, 0x58, 0x58, 0x04, 0x59, 0x57, 0x5a, 0x7b,
  429. 0xa1, 0x10, 0xa2, 0xab, 0xa3, 0x98, 0xa4, 0xc1, 0xa8, 0x8c, 0xa9, 0x05,
  430. 0xaa, 0x17, 0xab, 0x35, 0xac, 0x41, 0xad, 0x68, 0xae, 0x00, 0xaf, 0x00,
  431. 0xa0, 0x00
  432. },
  433. { /* TV_MODE_EIA */
  434. 0x30, 0x24, 0x31, 0x84, 0x32, 0x20, 0x33, 0x09, 0x34, 0xf0, 0x3e, 0x03,
  435. 0x3f, 0xff, 0x40, 0x64, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0xc8,
  436. 0x45, 0x02, 0x46, 0x00, 0x47, 0xfc, 0x48, 0x20, 0x49, 0x1c, 0x4a, 0x00,
  437. 0x4b, 0xa0, 0x4c, 0x00,
  438. 0x50, 0x04, 0x51, 0x48, 0x52, 0x83, 0x53, 0x63, 0x54, 0x68, 0x55, 0x73,
  439. 0x56, 0x57, 0x57, 0x58, 0x58, 0x04, 0x59, 0x57, 0x5a, 0x7b,
  440. 0xa1, 0x10, 0xa2, 0xab, 0xa3, 0x98, 0xa4, 0xc1, 0xa8, 0x8c, 0xa9, 0x05,
  441. 0xaa, 0x17, 0xab, 0x35, 0xac, 0x41, 0xad, 0x68, 0xae, 0x00, 0xaf, 0x00,
  442. 0xa0, 0x00
  443. },
  444. };
  445. static char SMI_GCR[18] = {
  446. 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40,
  447. 0x06, 0x05, 0x07, 0x0f, 0x08, 0xff
  448. };
  449. /*******************************************************************************
  450. *
  451. * Read SMI ISA register
  452. */
  453. static char smiRead (unsigned short index, char reg)
  454. {
  455. register GraphicDevice *pGD = (GraphicDevice *)&smi;
  456. out8 ((pGD->isaBase + index), reg);
  457. return (in8 (pGD->isaBase + index + 1));
  458. }
  459. /*******************************************************************************
  460. *
  461. * Write SMI ISA register
  462. */
  463. static void smiWrite (unsigned short index, char reg, char val)
  464. {
  465. register GraphicDevice *pGD = (GraphicDevice *)&smi;
  466. out8 ((pGD->isaBase + index), reg);
  467. out8 ((pGD->isaBase + index + 1), val);
  468. }
  469. /*******************************************************************************
  470. *
  471. * Write a table of SMI ISA register
  472. */
  473. static void smiLoadRegs (
  474. unsigned int iReg,
  475. unsigned int dReg,
  476. char *regTab,
  477. unsigned int tabSize
  478. )
  479. {
  480. register int i;
  481. for (i=0; i<tabSize; i+=2)
  482. {
  483. out8 (iReg, regTab[i]);
  484. out8 (dReg, regTab[i+1]);
  485. }
  486. }
  487. /*******************************************************************************
  488. *
  489. * Init capture port registers
  490. */
  491. static void smiInitCapturePort (void)
  492. {
  493. SmiCapturePort smiCP = { 0x01400600, 0x30, 0x40, 480, 640, 0, 0, 2560, 6 };
  494. register GraphicDevice *pGD = (GraphicDevice *)&smi;
  495. register SmiCapturePort *pCP = (SmiCapturePort *)&smiCP;
  496. out32r ((pGD->cprBase + 0x0004), ((pCP->topClip<<16) | pCP->leftClip));
  497. out32r ((pGD->cprBase + 0x0008), ((pCP->srcHeight<<16) | pCP->srcWidth));
  498. out32r ((pGD->cprBase + 0x000c), pCP->srcBufStart1/8);
  499. out32r ((pGD->cprBase + 0x0010), pCP->srcBufStart2/8);
  500. out32r ((pGD->cprBase + 0x0014), pCP->srcOffset/8);
  501. out32r ((pGD->cprBase + 0x0018), pCP->fifoControl);
  502. out32r ((pGD->cprBase + 0x0000), pCP->control);
  503. }
  504. /*******************************************************************************
  505. *
  506. * Init video processor registers
  507. */
  508. static void smiInitVideoProcessor (void)
  509. {
  510. SmiVideoProc smiVP = { 0x100000, 0, 0, 0, 0, 1600, 0x1200543, 4, 0xededed };
  511. SmiVideoWin smiVW = { 0, 0, 599, 799, 0, 1600, 0, 0, 0 };
  512. register GraphicDevice *pGD = (GraphicDevice *)&smi;
  513. register SmiVideoProc *pVP = (SmiVideoProc *)&smiVP;
  514. register SmiVideoWin *pVWin = (SmiVideoWin *)&smiVW;
  515. pVP->width = pGD->plnSizeX * pGD->gdfBytesPP;
  516. pVP->control |= pGD->gdfIndex << 16;
  517. pVWin->bottom = pGD->winSizeY - 1;
  518. pVWin->right = pGD->winSizeX - 1;
  519. pVWin->width = pVP->width;
  520. /* color key */
  521. out32r ((pGD->vprBase + 0x0004), pVP->colorKey);
  522. /* color key mask */
  523. out32r ((pGD->vprBase + 0x0008), pVP->colorKeyMask);
  524. /* data src start adrs */
  525. out32r ((pGD->vprBase + 0x000c), pVP->start / 8);
  526. /* data width and offset */
  527. out32r ((pGD->vprBase + 0x0010),
  528. ((pVP->offset / 8 * pGD->gdfBytesPP) << 16) |
  529. (pGD->plnSizeX / 8 * pGD->gdfBytesPP));
  530. /* video window 1 */
  531. out32r ((pGD->vprBase + 0x0014),
  532. ((pVWin->top << 16) | pVWin->left));
  533. out32r ((pGD->vprBase + 0x0018),
  534. ((pVWin->bottom << 16) | pVWin->right));
  535. out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8);
  536. out32r ((pGD->vprBase + 0x0020),
  537. (((pVWin->offset / 8) << 16) | (pVWin->width / 8)));
  538. out32r ((pGD->vprBase + 0x0024),
  539. (((pVWin->hStretch) << 8) | pVWin->vStretch));
  540. /* video window 2 */
  541. out32r ((pGD->vprBase + 0x0028),
  542. ((pVWin->top << 16) | pVWin->left));
  543. out32r ((pGD->vprBase + 0x002c),
  544. ((pVWin->bottom << 16) | pVWin->right));
  545. out32r ((pGD->vprBase + 0x0030),
  546. pVWin->srcStart / 8);
  547. out32r ((pGD->vprBase + 0x0034),
  548. (((pVWin->offset / 8) << 16) | (pVWin->width / 8)));
  549. out32r ((pGD->vprBase + 0x0038),
  550. (((pVWin->hStretch) << 8) | pVWin->vStretch));
  551. /* fifo prio control */
  552. out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio);
  553. /* fifo empty request levell */
  554. out32r ((pGD->vprBase + 0x0058), pVP->fifoERL);
  555. /* conversion constant */
  556. out32r ((pGD->vprBase + 0x005c), pVP->YUVtoRGB);
  557. /* vpr control word */
  558. out32r ((pGD->vprBase + 0x0000), pVP->control);
  559. }
  560. /******************************************************************************
  561. *
  562. * Init drawing engine registers
  563. */
  564. static void smiInitDrawingEngine (void)
  565. {
  566. GraphicDevice *pGD = (GraphicDevice *)&smi;
  567. unsigned int val;
  568. /* don't start now */
  569. out32r ((pGD->dprBase + 0x000c), 0x000f0000);
  570. /* set rop2 to copypen */
  571. val = 0xffff3ff0 & in32r ((pGD->dprBase + 0x000c));
  572. out32r ((pGD->dprBase + 0x000c), (val | 0x8000 | 0x0c));
  573. /* set clip rect */
  574. out32r ((pGD->dprBase + 0x002c), 0);
  575. out32r ((pGD->dprBase + 0x0030),
  576. ((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP ));
  577. /* src row pitch */
  578. val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010)));
  579. out32r ((pGD->dprBase + 0x0010),
  580. (val | pGD->plnSizeX * pGD->gdfBytesPP));
  581. /* dst row pitch */
  582. val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010)));
  583. out32r ((pGD->dprBase + 0x0010),
  584. (((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val));
  585. /* window width src/dst */
  586. out32r ((pGD->dprBase + 0x003c),
  587. (((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) |
  588. (pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)));
  589. out16r ((pGD->dprBase + 0x001e), 0x0000);
  590. /* src base adrs */
  591. out32r ((pGD->dprBase + 0x0040),
  592. (((pGD->frameAdrs/8) & 0x000fffff)));
  593. /* dst base adrs */
  594. out32r ((pGD->dprBase + 0x0044),
  595. (((pGD->frameAdrs/8) & 0x000fffff)));
  596. /* foreground color */
  597. out32r ((pGD->dprBase + 0x0014), pGD->fg);
  598. /* background color */
  599. out32r ((pGD->dprBase + 0x0018), pGD->bg);
  600. /* xcolor */
  601. out32r ((pGD->dprBase + 0x0020), 0x00ffffff);
  602. /* xcolor mask */
  603. out32r ((pGD->dprBase + 0x0024), 0x00ffffff);
  604. /* bit mask */
  605. out32r ((pGD->dprBase + 0x0028), 0x00ffffff);
  606. /* load mono pattern */
  607. out32r ((pGD->dprBase + 0x0034), 0);
  608. out32r ((pGD->dprBase + 0x0038), 0);
  609. }
  610. static struct pci_device_id supported[] = {
  611. { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_710 },
  612. { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_712 },
  613. { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_810 },
  614. { }
  615. };
  616. /*******************************************************************************
  617. *
  618. * Init video chip with common Linux graphic modes (lilo)
  619. */
  620. void *video_hw_init (void)
  621. {
  622. GraphicDevice *pGD = (GraphicDevice *)&smi;
  623. unsigned short device_id;
  624. pci_dev_t devbusfn;
  625. int videomode;
  626. unsigned int pci_mem_base, *vm, i;
  627. unsigned int gdfTab[] = { 1, 2, 2, 4, 3, 1 };
  628. char *penv;
  629. char *gdfModes[] =
  630. {
  631. "8 Bit Index Color",
  632. "15 Bit 5-5-5 RGB",
  633. "16 Bit 5-6-5 RGB",
  634. "32 Bit X-8-8-8 RGB",
  635. "24 Bit 8-8-8 RGB",
  636. "8 Bit 3-3-2 RGB"
  637. };
  638. int vgaModes[16][2] =
  639. {
  640. {769, -1}, {771, 0x00002}, {773, 0x00003}, {775, 0x00004},
  641. {784, -1}, {787, 0x10002}, {790, 0x10003}, {793, 0x10004},
  642. {785, -1}, {788, 0x20002}, {791, 0x20003}, {794, 0x20004},
  643. {786, -1}, {789, 0x40002}, {792, 0x40003}, {795, 0x40004}
  644. };
  645. /* Search for video chip */
  646. printf("Video: ");
  647. if ((devbusfn = pci_find_devices(supported, 0)) < 0)
  648. {
  649. printf ("Controller not found !\n");
  650. return (NULL);
  651. }
  652. /* PCI setup */
  653. pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
  654. pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
  655. pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
  656. pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
  657. /* Initialize the video controller */
  658. if ((penv = getenv ("videomode")) != NULL)
  659. videomode = (int)simple_strtoul (penv, NULL, 16);
  660. else
  661. videomode = 0x303; /* Default 800x600 8 bit index color */
  662. /* Compare with common vga mode numbers */
  663. for (i=0; i<16; i++)
  664. {
  665. if (vgaModes[i][0] == videomode)
  666. {
  667. if (vgaModes[i][1] == -1)
  668. {
  669. printf("Videomode not supported !\n");
  670. return (NULL); /* mode not supported */
  671. }
  672. pGD->mode = vgaModes[i][1]; /* use driver int. mode number */
  673. break;
  674. }
  675. }
  676. /* Extract graphic data format */
  677. pGD->gdfIndex = (pGD->mode & 0x00070000) >> 16;
  678. if (pGD->gdfIndex > 5)
  679. pGD->gdfIndex = 0;
  680. pGD->gdfBytesPP = gdfTab[pGD->gdfIndex];
  681. /* Extract graphic resolution */
  682. pGD->mode &= 0xf;
  683. /* Exit for not supported resolutions */
  684. if (((pGD->mode==DUAL_800_600) || (pGD->mode==DUAL_1024_768)) && (pGD->gdfBytesPP > 1))
  685. {
  686. printf ("Dual screen for 1BPP only !\n");
  687. return (NULL);
  688. }
  689. if ((pGD->mode==SINGLE_1280_1024) && (pGD->gdfBytesPP==4))
  690. {
  691. printf ("Out of memory !\n");
  692. return (NULL);
  693. }
  694. /* Set graphic parameters */
  695. switch (pGD->mode)
  696. {
  697. case DUAL_800_600:
  698. pGD->winSizeX = 800;
  699. pGD->winSizeY = 600;
  700. pGD->plnSizeX = 1600;
  701. pGD->plnSizeY = 600;
  702. sprintf (pGD->modeIdent, "Dual Screen 800x600 with %s", gdfModes[pGD->gdfIndex]);
  703. break;
  704. case DUAL_1024_768:
  705. pGD->winSizeX = 1024;
  706. pGD->winSizeY = 768;
  707. pGD->plnSizeX = 2048;
  708. pGD->plnSizeY = 768;
  709. sprintf (pGD->modeIdent, "Dual Screen 1024x768 with %s", gdfModes[pGD->gdfIndex]);
  710. break;
  711. case SINGLE_800_600:
  712. pGD->winSizeX = 800;
  713. pGD->winSizeY = 600;
  714. pGD->plnSizeX = 800;
  715. pGD->plnSizeY = 600;
  716. sprintf (pGD->modeIdent, "Single Screen 800x600 with %s", gdfModes[pGD->gdfIndex]);
  717. break;
  718. case SINGLE_1024_768:
  719. pGD->winSizeX = 1024;
  720. pGD->winSizeY = 768;
  721. pGD->plnSizeX = 1024;
  722. pGD->plnSizeY = 768;
  723. sprintf (pGD->modeIdent,"Single Screen 1024x768 with %s", gdfModes[pGD->gdfIndex]);
  724. break;
  725. case TV_MODE_CCIR:
  726. pGD->winSizeX = 720;
  727. pGD->winSizeY = 576;
  728. pGD->plnSizeX = 720;
  729. pGD->plnSizeY = 576;
  730. sprintf (pGD->modeIdent, "TV Mode CCIR with %s", gdfModes[pGD->gdfIndex]);
  731. break;
  732. case TV_MODE_EIA:
  733. pGD->winSizeX = 720;
  734. pGD->winSizeY = 484;
  735. pGD->plnSizeX = 720;
  736. pGD->plnSizeY = 484;
  737. sprintf (pGD->modeIdent, "TV Mode EIA with %s", gdfModes[pGD->gdfIndex]);
  738. break;
  739. case SINGLE_1280_1024:
  740. pGD->winSizeX = 1280;
  741. pGD->winSizeY = 1024;
  742. pGD->plnSizeX = 1280;
  743. pGD->plnSizeY = 1024;
  744. sprintf (pGD->modeIdent, "Single Screen 1280x1024 with %s", gdfModes[pGD->gdfIndex]);
  745. break;
  746. default:
  747. printf("Videomode not supported !\n");
  748. return (NULL);
  749. }
  750. pGD->isaBase = CFG_ISA_IO;
  751. pGD->pciBase = pci_mem_base;
  752. pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000);
  753. pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000);
  754. pGD->cprBase = (pci_mem_base + 0x400000 + 0xe000);
  755. pGD->frameAdrs = pci_mem_base;
  756. pGD->memSize = VIDEO_MEM_SIZE;
  757. /* Turn off display */
  758. smiWrite (0x3c4, 0x01, 0x20);
  759. /* Unlock ext. crt regs */
  760. out8 (SMI_LOCK_REG, 0x40);
  761. /* Set Register base to isa 3dx for 3?x regs (color mode) */
  762. out8 (SMI_MISC_REG, 0x2b);
  763. /* Unlock crt regs 0-7 */
  764. smiWrite (0x3d4, 0x11, 0x0e);
  765. /* Sytem Control Register */
  766. smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5,
  767. SMI_SCR, sizeof(SMI_SCR));
  768. /* extented CRT Register */
  769. smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5,
  770. SMI_EXT_CRT[pGD->mode], sizeof(SMI_EXT_CRT)/VIDEO_MODES);
  771. /* Sequencer Register */
  772. smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5,
  773. SMI_SEQR, sizeof(SMI_SEQR));
  774. /* Power Control Register */
  775. smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5,
  776. SMI_PCR[pGD->mode], sizeof(SMI_PCR)/VIDEO_MODES);
  777. /* Memory Control Register */
  778. smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5,
  779. SMI_MCR[pGD->mode], sizeof(SMI_MCR)/VIDEO_MODES);
  780. /* Clock Control Register */
  781. smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5,
  782. SMI_CCR[pGD->mode], sizeof(SMI_CCR)/VIDEO_MODES);
  783. /* Shadow VGA Register */
  784. smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5,
  785. SMI_SHVGA[pGD->mode], sizeof(SMI_SHVGA)/VIDEO_MODES);
  786. /* General Purpose Register */
  787. smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5,
  788. SMI_GPR[pGD->mode], sizeof(SMI_GPR)/VIDEO_MODES);
  789. /* Hardware Cusor Register */
  790. smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5,
  791. SMI_HCR[pGD->mode], sizeof(SMI_HCR)/VIDEO_MODES);
  792. /* Flat Panel Register */
  793. smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5,
  794. SMI_FPR[pGD->mode], sizeof(SMI_FPR)/VIDEO_MODES);
  795. /* CRTC Register */
  796. smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5,
  797. SMI_CRTCR[pGD->mode], sizeof(SMI_CRTCR)/VIDEO_MODES);
  798. /* Graphics Controller Register */
  799. smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF,
  800. SMI_GCR, sizeof(SMI_GCR));
  801. /* Patch memory and refresh settings for SMI710 */
  802. if (device_id == PCI_DEVICE_ID_SMI_710)
  803. {
  804. unsigned char reg = smiRead (0x3c4, 0x62);
  805. /* external memory disabled */
  806. smiWrite (0x3c4, 0x62, (reg & 0xfb));
  807. /* memory clock */
  808. smiWrite (0x3c4, 0x6a, 0x75);
  809. }
  810. /* Patch memory and refresh settings for SMI712 */
  811. if (device_id == PCI_DEVICE_ID_SMI_712)
  812. {
  813. unsigned char reg = smiRead (0x3c4, 0x62);
  814. /* IL runs at MCLK; 64bit bus; external memory disabled */
  815. smiWrite (0x3c4, 0x62, (reg | 0xc4));
  816. /* memory clock */
  817. smiWrite (0x3c4, 0x6a, 0x80);
  818. }
  819. /* Patch clock settings for SMI810 */
  820. if (device_id == PCI_DEVICE_ID_SMI_810)
  821. {
  822. /* clock control */
  823. smiWrite (0x3c4, 0x69, 0x03);
  824. }
  825. /* Video processor default setup */
  826. smiInitVideoProcessor ();
  827. /* Capture port default setup */
  828. smiInitCapturePort ();
  829. /* Drawing engine default setup */
  830. smiInitDrawingEngine ();
  831. /* Turn on display */
  832. smiWrite (0x3c4, 0x01, 0x01);
  833. /* Clear video memory */
  834. i = pGD->memSize/4;
  835. vm = (unsigned int *)pGD->pciBase;
  836. while(i--)
  837. *vm++ = 0;
  838. printf("mode=%x - %s\n", videomode, pGD->modeIdent);
  839. return ((void*)&smi);
  840. }
  841. /*******************************************************************************
  842. *
  843. * Drawing engine fill on screen region
  844. */
  845. void video_hw_rectfill (
  846. unsigned int bpp, /* bytes per pixel */
  847. unsigned int dst_x, /* dest pos x */
  848. unsigned int dst_y, /* dest pos y */
  849. unsigned int dim_x, /* frame width */
  850. unsigned int dim_y, /* frame height */
  851. unsigned int color /* fill color */
  852. )
  853. {
  854. register GraphicDevice *pGD = (GraphicDevice *)&smi;
  855. register unsigned int control;
  856. dim_x *= bpp;
  857. out32r ((pGD->dprBase + 0x0014), color);
  858. out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y));
  859. out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y));
  860. control = 0x0000ffff & in32r ((pGD->dprBase + 0x000c));
  861. control |= 0x80010000;
  862. out32r ((pGD->dprBase + 0x000c), control);
  863. /* Wait for drawing processor */
  864. do
  865. {
  866. out8 ((pGD->isaBase + 0x3c4), 0x16);
  867. } while (in8 (pGD->isaBase + 0x3c5) & 0x08);
  868. }
  869. /*******************************************************************************
  870. *
  871. * Drawing engine bitblt with screen region
  872. */
  873. void video_hw_bitblt (
  874. unsigned int bpp, /* bytes per pixel */
  875. unsigned int src_x, /* source pos x */
  876. unsigned int src_y, /* source pos y */
  877. unsigned int dst_x, /* dest pos x */
  878. unsigned int dst_y, /* dest pos y */
  879. unsigned int dim_x, /* frame width */
  880. unsigned int dim_y /* frame height */
  881. )
  882. {
  883. register GraphicDevice *pGD = (GraphicDevice *)&smi;
  884. register unsigned int control;
  885. dim_x *= bpp;
  886. if ((src_y<dst_y) || ((src_y==dst_y) && (src_x<dst_x)))
  887. {
  888. out32r ((pGD->dprBase + 0x0000), (((src_x+dim_x-1)<<16) | (src_y+dim_y-1)));
  889. out32r ((pGD->dprBase + 0x0004), (((dst_x+dim_x-1)<<16) | (dst_y+dim_y-1)));
  890. control = 0x88000000;
  891. }
  892. else
  893. {
  894. out32r ((pGD->dprBase + 0x0000), ((src_x<<16) | src_y));
  895. out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y));
  896. control = 0x80000000;
  897. }
  898. out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y));
  899. control |= (0x0000ffff & in32r ((pGD->dprBase + 0x000c)));
  900. out32r ((pGD->dprBase + 0x000c), control);
  901. /* Wait for drawing processor */
  902. do
  903. {
  904. out8 ((pGD->isaBase + 0x3c4), 0x16);
  905. } while (in8 (pGD->isaBase + 0x3c5) & 0x08);
  906. }
  907. /*******************************************************************************
  908. *
  909. * Set a RGB color in the LUT (8 bit index)
  910. */
  911. void video_set_lut (
  912. unsigned int index, /* color number */
  913. unsigned char r, /* red */
  914. unsigned char g, /* green */
  915. unsigned char b /* blue */
  916. )
  917. {
  918. register GraphicDevice *pGD = (GraphicDevice *)&smi;
  919. out8 (SMI_LUT_MASK, 0xff);
  920. out8 (SMI_LUT_START, (char)index);
  921. out8 (SMI_LUT_RGB, r>>2); /* red */
  922. udelay (10);
  923. out8 (SMI_LUT_RGB, g>>2); /* green */
  924. udelay (10);
  925. out8 (SMI_LUT_RGB, b>>2); /* blue */
  926. udelay (10);
  927. }
  928. #endif /* CONFIG_VIDEO_SMI_LYNXEM */