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uboot-vybrid_pu...
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board
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xilinx
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ml401
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xparameters.h

xparameters.h 2.1 KB
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  1. /*
    2. 

  2.  * (C) Copyright 2007 Michal Simek
    3. 

  3.  *
    4. 

  4.  * Michal  SIMEK <monstr@monstr.eu>
    5. 

  5.  *
    6. 

  6.  * See file CREDITS for list of people who contributed to this
    7. 

  7.  * project.
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or
    10. 

  10.  * modify it under the terms of the GNU General Public License as
    11. 

  11.  * published by the Free Software Foundation; either version 2 of
    12. 

  12.  * the License, or (at your option) any later version.
    13. 

  13.  *
    14. 

  14.  * This program is distributed in the hope that it will be useful,
    15. 

  15.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16. 

  16.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    17. 

  17.  * GNU General Public License for more details.
    18. 

  18.  *
    19. 

  19.  * You should have received a copy of the GNU General Public License
    20. 

  20.  * along with this program; if not, write to the Free Software
    21. 

  21.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    22. 

  22.  * MA 02111-1307 USA
    23. 

  23.  *
    24. 

  24.  *
    25. 

  25.  * CAUTION: This file is automatically generated by libgen.
    26. 

  26.  * Version: Xilinx EDK 6.3 EDK_Gmm.12.3
    27. 

  27.  */
    28. 

  28. 

  29. /* System Clock Frequency */
    30. 

  30. #define XILINX_CLOCK_FREQ	66666667
    31. 

  31. 

  32. /* Interrupt controller is intc_0 */
    33. 

  33. #define XILINX_INTC_BASEADDR	0xd1000fc0
    34. 

  34. #define XILINX_INTC_NUM_INTR_INPUTS	12
    35. 

  35. 

  36. /* Timer pheriphery is opb_timer_0 */
    37. 

  37. #define XILINX_TIMER_BASEADDR	0xa2000000
    38. 

  38. #define XILINX_TIMER_IRQ	0
    39. 

  39. 

  40. /* Uart pheriphery is console_uart */
    41. 

  41. #define XILINX_UART_BASEADDR	0xa0000000
    42. 

  42. #define XILINX_UART_BAUDRATE	115200
    43. 

  43. 

  44. /* GPIO is opb_gpio_0*/
    45. 

  45. #define XILINX_GPIO_BASEADDR	0x90000000
    46. 

  46. 

  47. /* Flash Memory is opb_emc_0 */
    48. 

  48. #define XILINX_FLASH_START	0x28000000
    49. 

  49. #define XILINX_FLASH_SIZE	0x00800000
    50. 

  50. 

  51. /* Main Memory is plb_ddr_0 */
    52. 

  52. #define XILINX_RAM_START	0x10000000
    53. 

  53. #define XILINX_RAM_SIZE	0x10000000
    54. 

  54. 

  55. /* Sysace Controller is opb_sysace_0 */
    56. 

  56. #define XILINX_SYSACE_BASEADDR	0xCF000000
    57. 

  57. #define XILINX_SYSACE_HIGHADDR	0xCF0001FF
    58. 

  58. #define XILINX_SYSACE_MEM_WIDTH	16
    59. 

  59. 

  60. /* Ethernet controller is opb_ethernet_0 */
    61. 

  61. #define XPAR_XEMAC_NUM_INSTANCES	1
    62. 

  62. #define XPAR_OPB_ETHERNET_0_DEVICE_ID	0
    63. 

  63. #define XPAR_OPB_ETHERNET_0_BASEADDR	0x60000000
    64. 

  64. #define XPAR_OPB_ETHERNET_0_HIGHADDR	0x60003FFF
    65. 

  65. #define XPAR_OPB_ETHERNET_0_DMA_PRESENT	1
    66. 

  66. #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST	1
    67. 

  67. #define XPAR_OPB_ETHERNET_0_MII_EXIST	1
    68.