start.S 2.6 KB

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  1. /*
  2. * Copyright (C) 2005-2006 Atmel Corporation
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <config.h>
  23. #include <asm/sysreg.h>
  24. #ifndef PART_SPECIFIC_BOOTSTRAP
  25. # define PART_SPECIFIC_BOOTSTRAP
  26. #endif
  27. #define SYSREG_MMUCR_I_OFFSET 2
  28. #define SYSREG_MMUCR_S_OFFSET 4
  29. #define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
  30. #define CPUCR_INIT (SYSREG_BIT(BI) | SYSREG_BIT(BE) \
  31. | SYSREG_BIT(FE) | SYSREG_BIT(RE) \
  32. | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
  33. .text
  34. .global _start
  35. _start:
  36. PART_SPECIFIC_BOOTSTRAP
  37. /* Reset the Status Register */
  38. mov r0, lo(SR_INIT)
  39. orh r0, hi(SR_INIT)
  40. mtsr SYSREG_SR, r0
  41. /* Reset CPUCR and invalidate the BTB */
  42. mov r2, CPUCR_INIT
  43. mtsr SYSREG_CPUCR, r2
  44. /* Flush the caches */
  45. mov r1, 0
  46. cache r1[4], 8
  47. cache r1[0], 0
  48. sync 0
  49. /* Reset the MMU to default settings */
  50. mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
  51. mtsr SYSREG_MMUCR, r0
  52. /* Internal RAM should not need any initialization. We might
  53. have to initialize external RAM here if the part doesn't
  54. have internal RAM (or we may use the data cache) */
  55. /* Jump to cacheable segment */
  56. lddpc pc, 1f
  57. .align 2
  58. 1: .long 2f
  59. 2: lddpc sp, sp_init
  60. /*
  61. * Relocate the data section and initialize .bss. Everything
  62. * is guaranteed to be at least doubleword aligned by the
  63. * linker script.
  64. */
  65. lddpc r12, .Ldata_vma
  66. lddpc r11, .Ldata_lma
  67. lddpc r10, .Ldata_end
  68. sub r10, r12
  69. 4: ld.d r8, r11++
  70. sub r10, 8
  71. st.d r12++, r8
  72. brne 4b
  73. mov r8, 0
  74. mov r9, 0
  75. lddpc r10, .Lbss_end
  76. sub r10, r12
  77. 4: sub r10, 8
  78. st.d r12++, r8
  79. brne 4b
  80. /* Initialize the GOT pointer */
  81. lddpc r6, got_init
  82. 3: rsub r6, pc
  83. ld.w pc, r6[board_init_f@got]
  84. .align 2
  85. .type sp_init,@object
  86. sp_init:
  87. .long CFG_INIT_SP_ADDR
  88. got_init:
  89. .long 3b - _GLOBAL_OFFSET_TABLE_
  90. .Ldata_lma:
  91. .long __data_lma
  92. .Ldata_vma:
  93. .long _data
  94. .Ldata_end:
  95. .long _edata
  96. .Lbss_end:
  97. .long _end