rmu.c 4.1 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <mpc8xx.h>
  25. /* ------------------------------------------------------------------------- */
  26. static long int dram_size (long int, long int *, long int);
  27. /* ------------------------------------------------------------------------- */
  28. #define _NOT_USED_ 0xFFFFCC25
  29. const uint sdram_table[] =
  30. {
  31. /*
  32. * Single Read. (Offset 00h in UPMA RAM)
  33. */
  34. 0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
  35. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  36. /*
  37. * Burst Read. (Offset 08h in UPMA RAM)
  38. */
  39. 0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
  40. 0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
  41. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  42. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  43. /*
  44. * Single Write. (Offset 18h in UPMA RAM)
  45. */
  46. 0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
  47. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  48. /*
  49. * Burst Write. (Offset 20h in UPMA RAM)
  50. */
  51. 0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
  52. 0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
  53. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  54. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  55. /*
  56. * Refresh. (Offset 30h in UPMA RAM)
  57. * (Initialization code at 0x36)
  58. */
  59. 0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
  60. _NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
  61. 0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4,
  62. /*
  63. * Exception. (Offset 3Ch in UPMA RAM)
  64. */
  65. 0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
  66. };
  67. /* ------------------------------------------------------------------------- */
  68. /*
  69. * Check Board Identity:
  70. */
  71. int checkboard (void)
  72. {
  73. puts ("Board: RMU\n") ;
  74. return (0) ;
  75. }
  76. /* ------------------------------------------------------------------------- */
  77. long int initdram (int board_type)
  78. {
  79. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  80. volatile memctl8xx_t *memctl = &immap->im_memctl;
  81. long int size9;
  82. upmconfig (UPMA, (uint *) sdram_table,
  83. sizeof (sdram_table) / sizeof (uint));
  84. /* Refresh clock prescalar */
  85. memctl->memc_mptpr = CFG_MPTPR;
  86. memctl->memc_mar = 0x00000088;
  87. /* Map controller banks 1 to the SDRAM bank */
  88. memctl->memc_or1 = CFG_OR1_PRELIM;
  89. memctl->memc_br1 = CFG_BR1_PRELIM;
  90. memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
  91. udelay (200);
  92. /* perform SDRAM initializsation sequence */
  93. memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */
  94. udelay (1);
  95. memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  96. udelay (1000);
  97. /* Check Bank 0 Memory Size,
  98. * 9 column mode
  99. */
  100. size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE_PRELIM,
  101. SDRAM_MAX_SIZE);
  102. /*
  103. * Final mapping:
  104. */
  105. memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
  106. udelay (1000);
  107. return (size9);
  108. }
  109. /* ------------------------------------------------------------------------- */
  110. /*
  111. * Check memory range for valid RAM. A simple memory test determines
  112. * the actually available RAM size between addresses `base' and
  113. * `base + maxsize'. Some (not all) hardware errors are detected:
  114. * - short between address lines
  115. * - short between data lines
  116. */
  117. static long int dram_size (long int mamr_value, long int *base,
  118. long int maxsize)
  119. {
  120. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  121. volatile memctl8xx_t *memctl = &immap->im_memctl;
  122. memctl->memc_mamr = mamr_value;
  123. return (get_ram_size(base, maxsize));
  124. }