glue.h 2.0 KB

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  1. #ifndef GLUE_H
  2. #define GLUE_H
  3. typedef unsigned int pci_dev_t;
  4. int mypci_find_device(int vendor, int product, int index);
  5. int mypci_bus(int device);
  6. int mypci_devfn(int device);
  7. unsigned long get_bar_size(pci_dev_t dev, int offset);
  8. u8 mypci_read_cfg_byte(int bus, int devfn, int offset);
  9. u16 mypci_read_cfg_word(int bus, int devfn, int offset);
  10. u32 mypci_read_cfg_long(int bus, int devfn, int offset);
  11. void mypci_write_cfg_byte(int bus, int devfn, int offset, u8 value);
  12. void mypci_write_cfg_word(int bus, int devfn, int offset, u16 value);
  13. void mypci_write_cfg_long(int bus, int devfn, int offset, u32 value);
  14. void _printf(const char *fmt, ...);
  15. char *_getenv(char *name);
  16. void *malloc(size_t size);
  17. void memset(void *addr, int value, size_t size);
  18. void memcpy(void *to, void *from, size_t numbytes);
  19. int strcmp(char *, char *);
  20. void enable_compatibility_hole(void);
  21. void disable_compatibility_hole(void);
  22. void map_rom(pci_dev_t dev, unsigned long address);
  23. void unmap_rom(pci_dev_t dev);
  24. int attempt_map_rom(pci_dev_t dev, void *copy_address);
  25. #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
  26. #define PCI_BASE_ADDRESS_SPACE_IO 0x01
  27. #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
  28. #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
  29. #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
  30. #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
  31. #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
  32. #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
  33. #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
  34. #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
  35. #define PCI_BUS(d) (((d) >> 16) & 0xff)
  36. #define PCI_DEV(d) (((d) >> 11) & 0x1f)
  37. #define PCI_FUNC(d) (((d) >> 8) & 0x7)
  38. #define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
  39. #define PCI_ANY_ID (~0)
  40. #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
  41. #define PCI_ROM_ADDRESS_ENABLE 0x01
  42. #define OFF(addr) ((addr) & 0xFFFF)
  43. #define SEG(addr) (((addr)>>4) &0xF000)
  44. #endif