eth.c 14 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <command.h>
  24. #include <netdev.h>
  25. #include <asm/mmu.h>
  26. #include <asm/processor.h>
  27. #include <asm/cache.h>
  28. #include <asm/immap_85xx.h>
  29. #include <asm/fsl_law.h>
  30. #include <asm/fsl_ddr_sdram.h>
  31. #include <asm/fsl_serdes.h>
  32. #include <asm/fsl_portals.h>
  33. #include <asm/fsl_liodn.h>
  34. #include <malloc.h>
  35. #include <fm_eth.h>
  36. #include <fsl_mdio.h>
  37. #include <miiphy.h>
  38. #include <phy.h>
  39. #include <asm/fsl_dtsec.h>
  40. #include <asm/fsl_serdes.h>
  41. #include "../common/qixis.h"
  42. #include "../common/fman.h"
  43. #include "t4240qds_qixis.h"
  44. #define EMI_NONE 0xFFFFFFFF
  45. #define EMI1_RGMII 0
  46. #define EMI1_SLOT1 1
  47. #define EMI1_SLOT2 2
  48. #define EMI1_SLOT3 3
  49. #define EMI1_SLOT4 4
  50. #define EMI1_SLOT5 5
  51. #define EMI1_SLOT7 7
  52. #define EMI2 8 /* tmp, FIXME */
  53. /* Slot6 and Slot8 do not have EMI connections */
  54. static int mdio_mux[NUM_FM_PORTS];
  55. static const char *mdio_names[] = {
  56. "T4240QDS_MDIO0",
  57. "T4240QDS_MDIO1",
  58. "T4240QDS_MDIO2",
  59. "T4240QDS_MDIO3",
  60. "T4240QDS_MDIO4",
  61. "T4240QDS_MDIO5",
  62. "NULL",
  63. "T4240QDS_MDIO7",
  64. "T4240QDS_10GC",
  65. };
  66. static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
  67. static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
  68. static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
  69. {
  70. return mdio_names[muxval];
  71. }
  72. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  73. {
  74. struct mii_dev *bus;
  75. const char *name = t4240qds_mdio_name_for_muxval(muxval);
  76. if (!name) {
  77. printf("No bus for muxval %x\n", muxval);
  78. return NULL;
  79. }
  80. bus = miiphy_get_dev_by_name(name);
  81. if (!bus) {
  82. printf("No bus by name %s\n", name);
  83. return NULL;
  84. }
  85. return bus;
  86. }
  87. struct t4240qds_mdio {
  88. u8 muxval;
  89. struct mii_dev *realbus;
  90. };
  91. static void t4240qds_mux_mdio(u8 muxval)
  92. {
  93. u8 brdcfg4;
  94. if ((muxval < 6) || (muxval == 7)) {
  95. brdcfg4 = QIXIS_READ(brdcfg[4]);
  96. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  97. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  98. QIXIS_WRITE(brdcfg[4], brdcfg4);
  99. }
  100. }
  101. static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
  102. int regnum)
  103. {
  104. struct t4240qds_mdio *priv = bus->priv;
  105. t4240qds_mux_mdio(priv->muxval);
  106. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  107. }
  108. static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  109. int regnum, u16 value)
  110. {
  111. struct t4240qds_mdio *priv = bus->priv;
  112. t4240qds_mux_mdio(priv->muxval);
  113. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  114. }
  115. static int t4240qds_mdio_reset(struct mii_dev *bus)
  116. {
  117. struct t4240qds_mdio *priv = bus->priv;
  118. return priv->realbus->reset(priv->realbus);
  119. }
  120. static int t4240qds_mdio_init(char *realbusname, u8 muxval)
  121. {
  122. struct t4240qds_mdio *pmdio;
  123. struct mii_dev *bus = mdio_alloc();
  124. if (!bus) {
  125. printf("Failed to allocate T4240QDS MDIO bus\n");
  126. return -1;
  127. }
  128. pmdio = malloc(sizeof(*pmdio));
  129. if (!pmdio) {
  130. printf("Failed to allocate T4240QDS private data\n");
  131. free(bus);
  132. return -1;
  133. }
  134. bus->read = t4240qds_mdio_read;
  135. bus->write = t4240qds_mdio_write;
  136. bus->reset = t4240qds_mdio_reset;
  137. sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
  138. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  139. if (!pmdio->realbus) {
  140. printf("No bus with name %s\n", realbusname);
  141. free(bus);
  142. free(pmdio);
  143. return -1;
  144. }
  145. pmdio->muxval = muxval;
  146. bus->priv = pmdio;
  147. return mdio_register(bus);
  148. }
  149. void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
  150. enum fm_port port, int offset)
  151. {
  152. if (mdio_mux[port] == EMI1_RGMII)
  153. fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
  154. /* TODO: will do with dts */
  155. }
  156. void fdt_fixup_board_enet(void *fdt)
  157. {
  158. /* TODO: will do with dts */
  159. }
  160. int board_eth_init(bd_t *bis)
  161. {
  162. #if defined(CONFIG_FMAN_ENET)
  163. int i;
  164. struct memac_mdio_info dtsec_mdio_info;
  165. struct memac_mdio_info tgec_mdio_info;
  166. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  167. u32 srds_prtcl_s1, srds_prtcl_s2;
  168. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  169. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  170. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  171. srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  172. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  173. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  174. /* Initialize the mdio_mux array so we can recognize empty elements */
  175. for (i = 0; i < NUM_FM_PORTS; i++)
  176. mdio_mux[i] = EMI_NONE;
  177. dtsec_mdio_info.regs =
  178. (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
  179. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  180. /* Register the 1G MDIO bus */
  181. fm_memac_mdio_init(bis, &dtsec_mdio_info);
  182. tgec_mdio_info.regs =
  183. (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
  184. tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  185. /* Register the 10G MDIO bus */
  186. fm_memac_mdio_init(bis, &tgec_mdio_info);
  187. /* Register the muxing front-ends to the MDIO buses */
  188. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
  189. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
  190. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
  191. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
  192. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
  193. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
  194. t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
  195. t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
  196. switch (srds_prtcl_s1) {
  197. case 1:
  198. case 2:
  199. case 4:
  200. /* XAUI/HiGig in Slot1 and Slot2 */
  201. fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  202. fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
  203. break;
  204. case 28:
  205. case 36:
  206. /* SGMII in Slot1 and Slot2 */
  207. fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  208. fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
  209. fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
  210. fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
  211. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  212. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  213. if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
  214. fm_info_set_phy_address(FM1_DTSEC9,
  215. SGMII_CARD_PORT4_PHY_ADDR);
  216. fm_info_set_phy_address(FM1_DTSEC10,
  217. SGMII_CARD_PORT3_PHY_ADDR);
  218. }
  219. break;
  220. case 38:
  221. fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
  222. fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
  223. if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
  224. fm_info_set_phy_address(FM1_DTSEC9,
  225. QSGMII_CARD_PHY_ADDR);
  226. fm_info_set_phy_address(FM1_DTSEC10,
  227. QSGMII_CARD_PHY_ADDR);
  228. }
  229. break;
  230. case 40:
  231. case 46:
  232. case 48:
  233. fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  234. fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  235. if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
  236. fm_info_set_phy_address(FM1_DTSEC10,
  237. SGMII_CARD_PORT3_PHY_ADDR);
  238. fm_info_set_phy_address(FM1_DTSEC9,
  239. SGMII_CARD_PORT4_PHY_ADDR);
  240. }
  241. fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
  242. fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
  243. fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
  244. fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
  245. break;
  246. default:
  247. puts("Invalid SerDes1 protocol for T4240QDS\n");
  248. break;
  249. }
  250. for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  251. int idx = i - FM1_DTSEC1, lane, slot;
  252. switch (fm_info_get_enet_if(i)) {
  253. case PHY_INTERFACE_MODE_SGMII:
  254. lane = serdes_get_first_lane(FSL_SRDS_1,
  255. SGMII_FM1_DTSEC1 + idx);
  256. if (lane < 0)
  257. break;
  258. slot = lane_to_slot_fsm1[lane];
  259. debug("FM1@DTSEC%u expects SGMII in slot %u\n",
  260. idx + 1, slot);
  261. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  262. fm_disable_port(i);
  263. switch (slot) {
  264. case 1:
  265. mdio_mux[i] = EMI1_SLOT1;
  266. fm_info_set_mdio(i,
  267. mii_dev_for_muxval(mdio_mux[i]));
  268. break;
  269. case 2:
  270. mdio_mux[i] = EMI1_SLOT2;
  271. fm_info_set_mdio(i,
  272. mii_dev_for_muxval(mdio_mux[i]));
  273. break;
  274. };
  275. break;
  276. case PHY_INTERFACE_MODE_RGMII:
  277. /* FM1 DTSEC5 routes to RGMII with EC2 */
  278. debug("FM1@DTSEC%u is RGMII at address %u\n",
  279. idx + 1, 2);
  280. if (i == FM1_DTSEC5)
  281. fm_info_set_phy_address(i, 2);
  282. mdio_mux[i] = EMI1_RGMII;
  283. fm_info_set_mdio(i,
  284. mii_dev_for_muxval(mdio_mux[i]));
  285. break;
  286. default:
  287. break;
  288. }
  289. }
  290. for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  291. switch (fm_info_get_enet_if(i)) {
  292. case PHY_INTERFACE_MODE_XGMII:
  293. mdio_mux[i] = EMI2;
  294. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  295. break;
  296. default:
  297. break;
  298. }
  299. }
  300. #if (CONFIG_SYS_NUM_FMAN == 2)
  301. switch (srds_prtcl_s2) {
  302. case 1:
  303. case 2:
  304. case 4:
  305. /* XAUI/HiGig in Slot3 and Slot4 */
  306. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  307. fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
  308. break;
  309. case 7:
  310. case 13:
  311. case 14:
  312. case 16:
  313. case 22:
  314. case 23:
  315. case 25:
  316. case 26:
  317. /* XAUI/HiGig in Slot3, SGMII in Slot4 */
  318. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  319. fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  320. fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
  321. fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
  322. fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
  323. break;
  324. case 28:
  325. case 36:
  326. /* SGMII in Slot3 and Slot4 */
  327. fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  328. fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
  329. fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
  330. fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
  331. fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  332. fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  333. fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
  334. fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  335. break;
  336. case 38:
  337. /* QSGMII in Slot3 and Slot4 */
  338. fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
  339. fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
  340. fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
  341. fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
  342. fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
  343. fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
  344. fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
  345. fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
  346. break;
  347. case 40:
  348. case 46:
  349. case 48:
  350. /* SGMII in Slot3 */
  351. fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
  352. fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
  353. fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
  354. fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
  355. /* QSGMII in Slot4 */
  356. fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
  357. fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
  358. fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
  359. fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
  360. break;
  361. case 50:
  362. case 52:
  363. case 54:
  364. fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
  365. fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
  366. fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
  367. fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
  368. fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
  369. break;
  370. case 56:
  371. case 57:
  372. /* XFI in Slot3, SGMII in Slot4 */
  373. fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
  374. fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
  375. fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
  376. fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
  377. fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
  378. fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
  379. fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
  380. fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
  381. break;
  382. default:
  383. puts("Invalid SerDes2 protocol for T4240QDS\n");
  384. break;
  385. }
  386. for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  387. int idx = i - FM2_DTSEC1, lane, slot;
  388. switch (fm_info_get_enet_if(i)) {
  389. case PHY_INTERFACE_MODE_SGMII:
  390. lane = serdes_get_first_lane(FSL_SRDS_2,
  391. SGMII_FM2_DTSEC1 + idx);
  392. if (lane < 0)
  393. break;
  394. slot = lane_to_slot_fsm2[lane];
  395. debug("FM2@DTSEC%u expects SGMII in slot %u\n",
  396. idx + 1, slot);
  397. if (QIXIS_READ(present2) & (1 << (slot - 1)))
  398. fm_disable_port(i);
  399. switch (slot) {
  400. case 3:
  401. mdio_mux[i] = EMI1_SLOT3;
  402. fm_info_set_mdio(i,
  403. mii_dev_for_muxval(mdio_mux[i]));
  404. break;
  405. case 4:
  406. mdio_mux[i] = EMI1_SLOT4;
  407. fm_info_set_mdio(i,
  408. mii_dev_for_muxval(mdio_mux[i]));
  409. break;
  410. };
  411. break;
  412. case PHY_INTERFACE_MODE_RGMII:
  413. /*
  414. * If DTSEC5 is RGMII, then it's routed via via EC1 to
  415. * the first on-board RGMII port. If DTSEC6 is RGMII,
  416. * then it's routed via via EC2 to the second on-board
  417. * RGMII port.
  418. */
  419. debug("FM2@DTSEC%u is RGMII at address %u\n",
  420. idx + 1, i == FM2_DTSEC5 ? 1 : 2);
  421. fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
  422. mdio_mux[i] = EMI1_RGMII;
  423. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  424. break;
  425. default:
  426. break;
  427. }
  428. }
  429. for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
  430. switch (fm_info_get_enet_if(i)) {
  431. case PHY_INTERFACE_MODE_XGMII:
  432. mdio_mux[i] = EMI2;
  433. fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
  434. break;
  435. default:
  436. break;
  437. }
  438. }
  439. #endif /* CONFIG_SYS_NUM_FMAN */
  440. cpu_eth_init(bis);
  441. #endif /* CONFIG_FMAN_ENET */
  442. return pci_eth_init(bis);
  443. }