pcippc2.c 4.1 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <config.h>
  24. #include <common.h>
  25. #include <command.h>
  26. #include <asm/io.h>
  27. #include <linux/mtd/doc2000.h>
  28. #include <watchdog.h>
  29. #include <pci.h>
  30. #include "hardware.h"
  31. #include "pcippc2.h"
  32. #include "sconsole.h"
  33. #include "fpga_serial.h"
  34. #if defined(CONFIG_WATCHDOG)
  35. static int pcippc2_wdt_init_done = 0;
  36. void pcippc2_wdt_init (void);
  37. #endif
  38. /* Check board identity
  39. */
  40. int checkboard (void)
  41. {
  42. #ifdef CONFIG_PCIPPC2
  43. puts ("Board: Gespac PCIPPC-2\n");
  44. #else
  45. puts ("Board: Gespac PCIPPC-6\n");
  46. #endif
  47. return 0;
  48. }
  49. /* RAM size is stored in CPC0_RGBAN1
  50. */
  51. u32 pcippc2_sdram_size (void)
  52. {
  53. return in32 (REG (CPC0, RGBAN1));
  54. }
  55. long initdram (int board_type)
  56. {
  57. return cpc710_ram_init ();
  58. }
  59. void do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  60. {
  61. out32 (REG (CPC0, SPOR), 0);
  62. iobarrier_rw ();
  63. while (1);
  64. }
  65. int board_pre_init (void)
  66. {
  67. out32 (REG (CPC0, RSTR), 0xC0000000);
  68. iobarrier_rw ();
  69. out32 (REG (CPC0, RSTR), 0xF0000000);
  70. iobarrier_rw ();
  71. out32 (REG (CPC0, UCTL), 0x00F80000);
  72. out32 (REG (CPC0, SIOC0), 0x30000000);
  73. out32 (REG (CPC0, ABCNTL), 0x00000000);
  74. out32 (REG (CPC0, SESR), 0x00000000);
  75. out32 (REG (CPC0, SEAR), 0x00000000);
  76. /* Detect IBM Avignon CPC710 Revision */
  77. if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
  78. out32 (REG (CPC0, PGCHP), 0xA0000040);
  79. else
  80. out32 (REG (CPC0, PGCHP), 0x80800040);
  81. out32 (REG (CPC0, ATAS), 0x709C2508);
  82. iobarrier_rw ();
  83. return 0;
  84. }
  85. void after_reloc (ulong dest_addr)
  86. {
  87. DECLARE_GLOBAL_DATA_PTR;
  88. /* Jump to the main U-Boot board init code
  89. */
  90. board_init_r (gd, dest_addr);
  91. }
  92. int misc_init_r (void)
  93. {
  94. pcippc2_fpga_init ();
  95. #if defined(CONFIG_WATCHDOG)
  96. pcippc2_wdt_init ();
  97. #endif
  98. fpga_serial_init (sconsole_get_baudrate ());
  99. sconsole_putc = fpga_serial_putc;
  100. sconsole_puts = fpga_serial_puts;
  101. sconsole_getc = fpga_serial_getc;
  102. sconsole_tstc = fpga_serial_tstc;
  103. sconsole_setbrg = fpga_serial_setbrg;
  104. sconsole_flush ();
  105. return (0);
  106. }
  107. void pci_init (void)
  108. {
  109. cpc710_pci_init ();
  110. /* FPGA requires no retry timeouts to be enabled
  111. */
  112. cpc710_pci_enable_timeout ();
  113. }
  114. void doc_init (void)
  115. {
  116. doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC);
  117. }
  118. #if defined(CONFIG_WATCHDOG)
  119. void pcippc2_wdt_init (void)
  120. {
  121. out16r (FPGA (WDT, PROG), 0xffff);
  122. out8 (FPGA (WDT, CTRL), 0x1);
  123. pcippc2_wdt_init_done = 1;
  124. }
  125. void pcippc2_wdt_done (void)
  126. {
  127. out8 (FPGA (WDT, CTRL), 0x0);
  128. pcippc2_wdt_init_done = 0;
  129. }
  130. void pcippc2_wdt_reset (void)
  131. {
  132. if (pcippc2_wdt_init_done == 1)
  133. out8 (FPGA (WDT, REFRESH), 0x56);
  134. }
  135. void watchdog_reset (void)
  136. {
  137. int re_enable = disable_interrupts ();
  138. pcippc2_wdt_reset ();
  139. if (re_enable)
  140. enable_interrupts ();
  141. }
  142. #if (CONFIG_COMMANDS & CFG_CMD_BSP)
  143. int do_wd (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  144. {
  145. switch (argc) {
  146. case 1:
  147. printf ("Watchdog timer status is %s\n",
  148. pcippc2_wdt_init_done == 1 ? "on" : "off");
  149. return 0;
  150. case 2:
  151. if (!strcmp(argv[1],"on")) {
  152. pcippc2_wdt_init();
  153. printf("Watchdog timer now is on\n");
  154. return 0;
  155. } else if (!strcmp(argv[1],"off")) {
  156. pcippc2_wdt_done();
  157. printf("Watchdog timer now is off\n");
  158. return 0;
  159. } else
  160. break;
  161. default:
  162. break;
  163. }
  164. printf ("Usage:\n%s\n", cmdtp->usage);
  165. return 1;
  166. }
  167. #endif /* CFG_CMD_BSP */
  168. #endif /* CONFIG_WATCHDOG */