ftmac110.c 11 KB

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  1. /*
  2. * Faraday 10/100Mbps Ethernet Controller
  3. *
  4. * (C) Copyright 2010 Faraday Technology
  5. * Dante Su <dantesu@faraday-tech.com>
  6. *
  7. * This file is released under the terms of GPL v2 and any later version.
  8. * See the file COPYING in the root directory of the source tree for details.
  9. */
  10. #include <common.h>
  11. #include <command.h>
  12. #include <malloc.h>
  13. #include <net.h>
  14. #include <asm/errno.h>
  15. #include <asm/io.h>
  16. #include <asm/dma-mapping.h>
  17. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  18. #include <miiphy.h>
  19. #endif
  20. #include "ftmac110.h"
  21. #define CFG_RXDES_NUM 8
  22. #define CFG_TXDES_NUM 2
  23. #define CFG_XBUF_SIZE 1536
  24. #define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
  25. #define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
  26. #define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
  27. /*
  28. * FTMAC110 DMA design issue
  29. *
  30. * Its DMA engine has a weird restriction that its Rx DMA engine
  31. * accepts only 16-bits aligned address, 32-bits aligned is not
  32. * acceptable. However this restriction does not apply to Tx DMA.
  33. *
  34. * Conclusion:
  35. * (1) Tx DMA Buffer Address:
  36. * 1 bytes aligned: Invalid
  37. * 2 bytes aligned: O.K
  38. * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
  39. * (2) Rx DMA Buffer Address:
  40. * 1 bytes aligned: Invalid
  41. * 2 bytes aligned: O.K
  42. * 4 bytes aligned: Invalid
  43. */
  44. struct ftmac110_chip {
  45. void __iomem *regs;
  46. uint32_t imr;
  47. uint32_t maccr;
  48. uint32_t lnkup;
  49. uint32_t phy_addr;
  50. struct ftmac110_rxd *rxd;
  51. ulong rxd_dma;
  52. uint32_t rxd_idx;
  53. struct ftmac110_txd *txd;
  54. ulong txd_dma;
  55. uint32_t txd_idx;
  56. };
  57. static int ftmac110_reset(struct eth_device *dev);
  58. static uint16_t mdio_read(struct eth_device *dev,
  59. uint8_t phyaddr, uint8_t phyreg)
  60. {
  61. struct ftmac110_chip *chip = dev->priv;
  62. struct ftmac110_regs __iomem *regs = chip->regs;
  63. uint32_t tmp, ts;
  64. uint16_t ret = 0xffff;
  65. tmp = PHYCR_READ
  66. | (phyaddr << PHYCR_ADDR_SHIFT)
  67. | (phyreg << PHYCR_REG_SHIFT);
  68. writel(tmp, &regs->phycr);
  69. for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
  70. tmp = readl(&regs->phycr);
  71. if (tmp & PHYCR_READ)
  72. continue;
  73. break;
  74. }
  75. if (tmp & PHYCR_READ)
  76. printf("ftmac110: mdio read timeout\n");
  77. else
  78. ret = (uint16_t)(tmp & 0xffff);
  79. return ret;
  80. }
  81. static void mdio_write(struct eth_device *dev,
  82. uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
  83. {
  84. struct ftmac110_chip *chip = dev->priv;
  85. struct ftmac110_regs __iomem *regs = chip->regs;
  86. uint32_t tmp, ts;
  87. tmp = PHYCR_WRITE
  88. | (phyaddr << PHYCR_ADDR_SHIFT)
  89. | (phyreg << PHYCR_REG_SHIFT);
  90. writel(phydata, &regs->phydr);
  91. writel(tmp, &regs->phycr);
  92. for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
  93. if (readl(&regs->phycr) & PHYCR_WRITE)
  94. continue;
  95. break;
  96. }
  97. if (readl(&regs->phycr) & PHYCR_WRITE)
  98. printf("ftmac110: mdio write timeout\n");
  99. }
  100. static uint32_t ftmac110_phyqry(struct eth_device *dev)
  101. {
  102. ulong ts;
  103. uint32_t maccr;
  104. uint16_t pa, tmp, bmsr, bmcr;
  105. struct ftmac110_chip *chip = dev->priv;
  106. /* Default = 100Mbps Full */
  107. maccr = MACCR_100M | MACCR_FD;
  108. /* 1. find the phy device */
  109. for (pa = 0; pa < 32; ++pa) {
  110. tmp = mdio_read(dev, pa, MII_PHYSID1);
  111. if (tmp == 0xFFFF || tmp == 0x0000)
  112. continue;
  113. chip->phy_addr = pa;
  114. break;
  115. }
  116. if (pa >= 32) {
  117. puts("ftmac110: phy device not found!\n");
  118. goto exit;
  119. }
  120. /* 2. wait until link-up & auto-negotiation complete */
  121. chip->lnkup = 0;
  122. bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
  123. ts = get_timer(0);
  124. do {
  125. bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
  126. chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
  127. if (!chip->lnkup)
  128. continue;
  129. if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
  130. break;
  131. } while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
  132. if (!chip->lnkup) {
  133. puts("ftmac110: link down\n");
  134. goto exit;
  135. }
  136. if (!(bmcr & BMCR_ANENABLE))
  137. puts("ftmac110: auto negotiation disabled\n");
  138. else if (!(bmsr & BMSR_ANEGCOMPLETE))
  139. puts("ftmac110: auto negotiation timeout\n");
  140. /* 3. derive MACCR */
  141. if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
  142. tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
  143. tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
  144. if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
  145. maccr = MACCR_100M | MACCR_FD;
  146. else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
  147. maccr = MACCR_100M;
  148. else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
  149. maccr = MACCR_FD;
  150. else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
  151. maccr = 0;
  152. } else {
  153. if (bmcr & BMCR_SPEED100)
  154. maccr = MACCR_100M;
  155. else
  156. maccr = 0;
  157. if (bmcr & BMCR_FULLDPLX)
  158. maccr |= MACCR_FD;
  159. }
  160. exit:
  161. printf("ftmac110: %d Mbps, %s\n",
  162. (maccr & MACCR_100M) ? 100 : 10,
  163. (maccr & MACCR_FD) ? "Full" : "half");
  164. return maccr;
  165. }
  166. static int ftmac110_reset(struct eth_device *dev)
  167. {
  168. uint8_t *a;
  169. uint32_t i, maccr;
  170. struct ftmac110_chip *chip = dev->priv;
  171. struct ftmac110_regs __iomem *regs = chip->regs;
  172. /* 1. MAC reset */
  173. writel(MACCR_RESET, &regs->maccr);
  174. for (i = get_timer(0); get_timer(i) < 1000; ) {
  175. if (readl(&regs->maccr) & MACCR_RESET)
  176. continue;
  177. break;
  178. }
  179. if (readl(&regs->maccr) & MACCR_RESET) {
  180. printf("ftmac110: reset failed\n");
  181. return -ENXIO;
  182. }
  183. /* 1-1. Init tx ring */
  184. for (i = 0; i < CFG_TXDES_NUM; ++i) {
  185. /* owned by SW */
  186. chip->txd[i].ct[0] = 0;
  187. }
  188. chip->txd_idx = 0;
  189. /* 1-2. Init rx ring */
  190. for (i = 0; i < CFG_RXDES_NUM; ++i) {
  191. /* owned by HW */
  192. chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
  193. }
  194. chip->rxd_idx = 0;
  195. /* 2. PHY status query */
  196. maccr = ftmac110_phyqry(dev);
  197. /* 3. Fix up the MACCR value */
  198. chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
  199. | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;
  200. /* 4. MAC address setup */
  201. a = dev->enetaddr;
  202. writel(a[1] | (a[0] << 8), &regs->mac[0]);
  203. writel(a[5] | (a[4] << 8) | (a[3] << 16)
  204. | (a[2] << 24), &regs->mac[1]);
  205. /* 5. MAC registers setup */
  206. writel(chip->rxd_dma, &regs->rxba);
  207. writel(chip->txd_dma, &regs->txba);
  208. /* interrupt at each tx/rx */
  209. writel(ITC_DEFAULT, &regs->itc);
  210. /* no tx pool, rx poll = 1 normal cycle */
  211. writel(APTC_DEFAULT, &regs->aptc);
  212. /* rx threshold = [6/8 fifo, 2/8 fifo] */
  213. writel(DBLAC_DEFAULT, &regs->dblac);
  214. /* disable & clear all interrupt status */
  215. chip->imr = 0;
  216. writel(ISR_ALL, &regs->isr);
  217. writel(chip->imr, &regs->imr);
  218. /* enable mac */
  219. writel(chip->maccr, &regs->maccr);
  220. return 0;
  221. }
  222. static int ftmac110_probe(struct eth_device *dev, bd_t *bis)
  223. {
  224. debug("ftmac110: probe\n");
  225. if (ftmac110_reset(dev))
  226. return -1;
  227. return 0;
  228. }
  229. static void ftmac110_halt(struct eth_device *dev)
  230. {
  231. struct ftmac110_chip *chip = dev->priv;
  232. struct ftmac110_regs __iomem *regs = chip->regs;
  233. writel(0, &regs->imr);
  234. writel(0, &regs->maccr);
  235. debug("ftmac110: halt\n");
  236. }
  237. static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
  238. {
  239. struct ftmac110_chip *chip = dev->priv;
  240. struct ftmac110_regs __iomem *regs = chip->regs;
  241. struct ftmac110_txd *des;
  242. if (!chip->lnkup)
  243. return 0;
  244. if (len <= 0 || len > CFG_XBUF_SIZE) {
  245. printf("ftmac110: bad tx pkt len(%d)\n", len);
  246. return 0;
  247. }
  248. len = max(60, len);
  249. des = &chip->txd[chip->txd_idx];
  250. if (le32_to_cpu(des->ct[0]) & FTMAC110_TXCT0_OWNER) {
  251. /* kick-off Tx DMA */
  252. writel(0xffffffff, &regs->txpd);
  253. printf("ftmac110: out of txd\n");
  254. return 0;
  255. }
  256. memcpy(des->vbuf, (void *)pkt, len);
  257. dma_map_single(des->vbuf, len, DMA_TO_DEVICE);
  258. /* update len, fts and lts */
  259. des->ct[1] &= cpu_to_le32(FTMAC110_TXCT1_END);
  260. des->ct[1] |= cpu_to_le32(FTMAC110_TXCT1_LEN(len)
  261. | FTMAC110_TXCT1_FTS | FTMAC110_TXCT1_LTS);
  262. /* set owner bit and clear others */
  263. des->ct[0] = cpu_to_le32(FTMAC110_TXCT0_OWNER);
  264. /* kick-off Tx DMA */
  265. writel(0xffffffff, &regs->txpd);
  266. chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
  267. return len;
  268. }
  269. static int ftmac110_recv(struct eth_device *dev)
  270. {
  271. struct ftmac110_chip *chip = dev->priv;
  272. struct ftmac110_rxd *des;
  273. uint32_t ct0, len, rlen = 0;
  274. uint8_t *buf;
  275. if (!chip->lnkup)
  276. return 0;
  277. do {
  278. des = &chip->rxd[chip->rxd_idx];
  279. ct0 = le32_to_cpu(des->ct[0]);
  280. if (ct0 & FTMAC110_RXCT0_OWNER)
  281. break;
  282. len = FTMAC110_RXCT0_LEN(ct0);
  283. buf = des->vbuf;
  284. if (ct0 & FTMAC110_RXCT0_ERRMASK) {
  285. printf("ftmac110: rx error\n");
  286. } else {
  287. dma_map_single(buf, len, DMA_FROM_DEVICE);
  288. NetReceive(buf, len);
  289. rlen += len;
  290. }
  291. /* owned by hardware */
  292. des->ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
  293. chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
  294. } while (0);
  295. return rlen;
  296. }
  297. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  298. static int ftmac110_mdio_read(
  299. const char *devname, uint8_t addr, uint8_t reg, uint16_t *value)
  300. {
  301. int ret = 0;
  302. struct eth_device *dev;
  303. dev = eth_get_dev_by_name(devname);
  304. if (dev == NULL) {
  305. printf("%s: no such device\n", devname);
  306. ret = -1;
  307. } else {
  308. *value = mdio_read(dev, addr, reg);
  309. }
  310. return ret;
  311. }
  312. static int ftmac110_mdio_write(
  313. const char *devname, uint8_t addr, uint8_t reg, uint16_t value)
  314. {
  315. int ret = 0;
  316. struct eth_device *dev;
  317. dev = eth_get_dev_by_name(devname);
  318. if (dev == NULL) {
  319. printf("%s: no such device\n", devname);
  320. ret = -1;
  321. } else {
  322. mdio_write(dev, addr, reg, value);
  323. }
  324. return ret;
  325. }
  326. #endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
  327. int ftmac110_initialize(bd_t *bis)
  328. {
  329. int i, card_nr = 0;
  330. struct eth_device *dev;
  331. struct ftmac110_chip *chip;
  332. dev = malloc(sizeof(*dev) + sizeof(*chip));
  333. if (dev == NULL) {
  334. panic("ftmac110: out of memory 1\n");
  335. return -1;
  336. }
  337. chip = (struct ftmac110_chip *)(dev + 1);
  338. memset(dev, 0, sizeof(*dev) + sizeof(*chip));
  339. sprintf(dev->name, "FTMAC110#%d", card_nr);
  340. dev->iobase = CONFIG_FTMAC110_BASE;
  341. chip->regs = (void __iomem *)dev->iobase;
  342. dev->priv = chip;
  343. dev->init = ftmac110_probe;
  344. dev->halt = ftmac110_halt;
  345. dev->send = ftmac110_send;
  346. dev->recv = ftmac110_recv;
  347. if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr))
  348. eth_random_enetaddr(dev->enetaddr);
  349. /* allocate tx descriptors (it must be 16 bytes aligned) */
  350. chip->txd = dma_alloc_coherent(
  351. sizeof(struct ftmac110_txd) * CFG_TXDES_NUM, &chip->txd_dma);
  352. if (!chip->txd)
  353. panic("ftmac110: out of memory 3\n");
  354. memset(chip->txd, 0,
  355. sizeof(struct ftmac110_txd) * CFG_TXDES_NUM);
  356. for (i = 0; i < CFG_TXDES_NUM; ++i) {
  357. void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
  358. if (!va)
  359. panic("ftmac110: out of memory 4\n");
  360. chip->txd[i].vbuf = va;
  361. chip->txd[i].buf = cpu_to_le32(virt_to_phys(va));
  362. chip->txd[i].ct[1] = 0;
  363. chip->txd[i].ct[0] = 0; /* owned by SW */
  364. }
  365. chip->txd[i - 1].ct[1] |= cpu_to_le32(FTMAC110_TXCT1_END);
  366. chip->txd_idx = 0;
  367. /* allocate rx descriptors (it must be 16 bytes aligned) */
  368. chip->rxd = dma_alloc_coherent(
  369. sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM, &chip->rxd_dma);
  370. if (!chip->rxd)
  371. panic("ftmac110: out of memory 4\n");
  372. memset((void *)chip->rxd, 0,
  373. sizeof(struct ftmac110_rxd) * CFG_RXDES_NUM);
  374. for (i = 0; i < CFG_RXDES_NUM; ++i) {
  375. void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
  376. if (!va)
  377. panic("ftmac110: out of memory 5\n");
  378. /* it needs to be exactly 2 bytes aligned */
  379. va = ((uint8_t *)va + 2);
  380. chip->rxd[i].vbuf = va;
  381. chip->rxd[i].buf = cpu_to_le32(virt_to_phys(va));
  382. chip->rxd[i].ct[1] = cpu_to_le32(CFG_XBUF_SIZE);
  383. chip->rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
  384. }
  385. chip->rxd[i - 1].ct[1] |= cpu_to_le32(FTMAC110_RXCT1_END);
  386. chip->rxd_idx = 0;
  387. eth_register(dev);
  388. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  389. miiphy_register(dev->name, ftmac110_mdio_read, ftmac110_mdio_write);
  390. #endif
  391. card_nr++;
  392. return card_nr;
  393. }