tegra2-common.h 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178
  1. /*
  2. * (C) Copyright 2010,2011
  3. * NVIDIA Corporation <www.nvidia.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __TEGRA2_COMMON_H
  24. #define __TEGRA2_COMMON_H
  25. #include <asm/sizes.h>
  26. /*
  27. * High Level Configuration Options
  28. */
  29. #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
  30. #define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
  31. #define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
  32. #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
  33. #define CONFIG_SYS_CACHELINE_SIZE 32
  34. #define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */
  35. #include <asm/arch/tegra2.h> /* get chip and board defs */
  36. /*
  37. * Display CPU and Board information
  38. */
  39. #define CONFIG_DISPLAY_CPUINFO
  40. #define CONFIG_DISPLAY_BOARDINFO
  41. #define CONFIG_SKIP_LOWLEVEL_INIT
  42. #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
  43. #define CONFIG_OF_LIBFDT /* enable passing of devicetree */
  44. /* Environment */
  45. #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
  46. /*
  47. * Size of malloc() pool
  48. */
  49. #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
  50. /*
  51. * PllX Configuration
  52. */
  53. #define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
  54. /*
  55. * NS16550 Configuration
  56. */
  57. #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
  58. #define CONFIG_SYS_NS16550
  59. #define CONFIG_SYS_NS16550_SERIAL
  60. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  61. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  62. /*
  63. * select serial console configuration
  64. */
  65. #define CONFIG_CONS_INDEX 1
  66. /* allow to overwrite serial and ethaddr */
  67. #define CONFIG_ENV_OVERWRITE
  68. #define CONFIG_BAUDRATE 115200
  69. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  70. 115200}
  71. /*
  72. * This parameter affects a TXFILLTUNING field that controls how much data is
  73. * sent to the latency fifo before it is sent to the wire. Without this
  74. * parameter, the default (2) causes occasional Data Buffer Errors in OUT
  75. * packets depending on the buffer address and size.
  76. */
  77. #define CONFIG_USB_EHCI_TXFIFO_THRESH 10
  78. #define CONFIG_EHCI_IS_TDI
  79. #define CONFIG_EHCI_DCACHE
  80. /* Total I2C ports on Tegra2 */
  81. #define TEGRA_I2C_NUM_CONTROLLERS 4
  82. /* include default commands */
  83. #include <config_cmd_default.h>
  84. /* remove unused commands */
  85. #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  86. #undef CONFIG_CMD_FPGA /* FPGA configuration support */
  87. #undef CONFIG_CMD_IMI
  88. #undef CONFIG_CMD_IMLS
  89. #undef CONFIG_CMD_NFS /* NFS support */
  90. #undef CONFIG_CMD_NET /* network support */
  91. /* turn on command-line edit/hist/auto */
  92. #define CONFIG_CMDLINE_EDITING
  93. #define CONFIG_COMMAND_HISTORY
  94. #define CONFIG_AUTO_COMPLETE
  95. #define CONFIG_SYS_NO_FLASH
  96. /* Environment information */
  97. #define CONFIG_EXTRA_ENV_SETTINGS \
  98. "console=ttyS0,115200n8\0" \
  99. "mem=" TEGRA2_SYSMEM "\0" \
  100. "smpflag=smp\0" \
  101. #define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
  102. #define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
  103. /*
  104. * Miscellaneous configurable options
  105. */
  106. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  107. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  108. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  109. #define CONFIG_SYS_PROMPT V_PROMPT
  110. /*
  111. * Increasing the size of the IO buffer as default nfsargs size is more
  112. * than 256 and so it is not possible to edit it
  113. */
  114. #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
  115. /* Print Buffer Size */
  116. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  117. sizeof(CONFIG_SYS_PROMPT) + 16)
  118. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  119. /* Boot Argument Buffer Size */
  120. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  121. #define CONFIG_SYS_MEMTEST_START (TEGRA2_SDRC_CS0 + 0x600000)
  122. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
  123. #define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
  124. #define CONFIG_SYS_HZ 1000
  125. /*-----------------------------------------------------------------------
  126. * Stack sizes
  127. *
  128. * The stack sizes are set up in start.S using the settings below
  129. */
  130. #define CONFIG_STACKBASE 0x2800000 /* 40MB */
  131. #define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/
  132. /*-----------------------------------------------------------------------
  133. * Physical Memory Map
  134. */
  135. #define CONFIG_NR_DRAM_BANKS 1
  136. #define PHYS_SDRAM_1 TEGRA2_SDRC_CS0
  137. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
  138. #define CONFIG_SYS_TEXT_BASE 0x00108000
  139. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  140. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
  141. #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
  142. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  143. CONFIG_SYS_INIT_RAM_SIZE - \
  144. GENERATED_GBL_DATA_SIZE)
  145. #define CONFIG_TEGRA2_GPIO
  146. #define CONFIG_CMD_GPIO
  147. #endif /* __TEGRA2_COMMON_H */