common.c 4.4 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <mpc8260.h>
  25. #include <ioports.h>
  26. #include <malloc.h>
  27. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  28. #include <libfdt.h>
  29. #endif
  30. #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
  31. #include <i2c.h>
  32. #endif
  33. extern int i2c_soft_read_pin (void);
  34. #if defined(CFG_I2C_INIT_BOARD)
  35. #define DELAY_ABORT_SEQ 62
  36. #define DELAY_HALF_PERIOD (500 / (CFG_I2C_SPEED / 1000))
  37. #if defined(CONFIG_MGCOGE)
  38. #define SDA_MASK 0x00010000
  39. #define SCL_MASK 0x00020000
  40. static void set_pin (int state, unsigned long mask)
  41. {
  42. volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
  43. if (state)
  44. iop->pdat |= (mask);
  45. else
  46. iop->pdat &= ~(mask);
  47. iop->pdir |= (mask);
  48. }
  49. static int get_pin (unsigned long mask)
  50. {
  51. volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
  52. iop->pdir &= ~(mask);
  53. return (0 != (iop->pdat & (mask)));
  54. }
  55. static void set_sda (int state)
  56. {
  57. set_pin (state, SDA_MASK);
  58. }
  59. static void set_scl (int state)
  60. {
  61. set_pin (state, SCL_MASK);
  62. }
  63. static int get_sda (void)
  64. {
  65. return get_pin (SDA_MASK);
  66. }
  67. static int get_scl (void)
  68. {
  69. return get_pin (SCL_MASK);
  70. }
  71. #if defined(CONFIG_HARD_I2C)
  72. static void setports (int gpio)
  73. {
  74. volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
  75. if (gpio) {
  76. iop->ppar &= ~(SDA_MASK | SCL_MASK);
  77. iop->podr &= ~(SDA_MASK | SCL_MASK);
  78. } else {
  79. iop->ppar |= (SDA_MASK | SCL_MASK);
  80. iop->pdir &= ~(SDA_MASK | SCL_MASK);
  81. iop->podr |= (SDA_MASK | SCL_MASK);
  82. }
  83. }
  84. #endif
  85. #endif
  86. #if defined(CONFIG_MGSUVD)
  87. static void set_sda (int state)
  88. {
  89. I2C_SDA(state);
  90. }
  91. static void set_scl (int state)
  92. {
  93. I2C_SCL(state);
  94. }
  95. static int get_sda (void)
  96. {
  97. return i2c_soft_read_pin ();
  98. }
  99. static int get_scl (void)
  100. {
  101. int val;
  102. *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF;
  103. udelay (1);
  104. val = *(unsigned char *)(I2C_BASE_PORT);
  105. return ((val & SCL_BIT) == SCL_BIT);
  106. }
  107. #endif
  108. static void writeStartSeq (void)
  109. {
  110. set_sda (1);
  111. udelay (DELAY_HALF_PERIOD);
  112. set_scl (1);
  113. udelay (DELAY_HALF_PERIOD);
  114. set_sda (0);
  115. udelay (DELAY_HALF_PERIOD);
  116. set_scl (0);
  117. udelay (DELAY_HALF_PERIOD);
  118. }
  119. /* I2C is a synchronous protocol and resets of the processor in the middle
  120. of an access can block the I2C Bus until a powerdown of the full unit is
  121. done. This function toggles the SCL until the SCL and SCA line are
  122. released, but max. 16 times, after this a I2C start-sequence is sent.
  123. This I2C Deblocking mechanism was developed by Keymile in association
  124. with Anatech and Atmel in 1998.
  125. */
  126. static int i2c_make_abort (void)
  127. {
  128. int scl_state = 0;
  129. int sda_state = 0;
  130. int i = 0;
  131. int ret = 0;
  132. if (!get_sda ()) {
  133. ret = -1;
  134. while (i < 16) {
  135. i++;
  136. set_scl (0);
  137. udelay (DELAY_ABORT_SEQ);
  138. set_scl (1);
  139. udelay (DELAY_ABORT_SEQ);
  140. scl_state = get_scl ();
  141. sda_state = get_sda ();
  142. if (scl_state && sda_state) {
  143. ret = 0;
  144. break;
  145. }
  146. }
  147. }
  148. if (ret == 0) {
  149. for (i =0; i < 5; i++) {
  150. writeStartSeq ();
  151. }
  152. }
  153. get_sda ();
  154. return ret;
  155. }
  156. /**
  157. * i2c_init_board - reset i2c bus. When the board is powercycled during a
  158. * bus transfer it might hang; for details see doc/I2C_Edge_Conditions.
  159. */
  160. void i2c_init_board(void)
  161. {
  162. #if defined(CONFIG_HARD_I2C)
  163. volatile immap_t *immap = (immap_t *)CFG_IMMR ;
  164. volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
  165. /* disable I2C controller first, otherwhise it thinks we want to */
  166. /* talk to the slave port... */
  167. i2c->i2c_i2mod &= ~0x01;
  168. /* Set the PortPins to GPIO */
  169. setports (1);
  170. #endif
  171. /* Now run the AbortSequence() */
  172. i2c_make_abort ();
  173. #if defined(CONFIG_HARD_I2C)
  174. /* Set the PortPins back to use for I2C */
  175. setports (0);
  176. #endif
  177. }
  178. #endif