44x_spd_ddr2.c 101 KB

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  1. /*
  2. * cpu/ppc4xx/44x_spd_ddr2.c
  3. * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
  4. * DDR2 controller (non Denali Core). Those currently are:
  5. *
  6. * 405: 405EX(r)
  7. * 440/460: 440SP/440SPe/460EX/460GT
  8. *
  9. * Copyright (c) 2008 Nuovation System Designs, LLC
  10. * Grant Erickson <gerickson@nuovations.com>
  11. * (C) Copyright 2007-2008
  12. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13. *
  14. * COPYRIGHT AMCC CORPORATION 2004
  15. *
  16. * See file CREDITS for list of people who contributed to this
  17. * project.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License as
  21. * published by the Free Software Foundation; either version 2 of
  22. * the License, or (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32. * MA 02111-1307 USA
  33. *
  34. */
  35. /* define DEBUG for debugging output (obviously ;-)) */
  36. #if 0
  37. #define DEBUG
  38. #endif
  39. #include <common.h>
  40. #include <command.h>
  41. #include <ppc4xx.h>
  42. #include <i2c.h>
  43. #include <asm/io.h>
  44. #include <asm/processor.h>
  45. #include <asm/mmu.h>
  46. #include <asm/cache.h>
  47. #include "ecc.h"
  48. #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
  49. #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
  50. do { \
  51. u32 data; \
  52. mfsdram(SDRAM_##mnemonic, data); \
  53. printf("%20s[%02x] = 0x%08X\n", \
  54. "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
  55. } while (0)
  56. #if defined(CONFIG_SPD_EEPROM)
  57. /*-----------------------------------------------------------------------------+
  58. * Defines
  59. *-----------------------------------------------------------------------------*/
  60. #ifndef TRUE
  61. #define TRUE 1
  62. #endif
  63. #ifndef FALSE
  64. #define FALSE 0
  65. #endif
  66. #define SDRAM_DDR1 1
  67. #define SDRAM_DDR2 2
  68. #define SDRAM_NONE 0
  69. #define MAXDIMMS 2
  70. #define MAXRANKS 4
  71. #define MAXBXCF 4
  72. #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
  73. #define ONE_BILLION 1000000000
  74. #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  75. #define CMD_NOP (7 << 19)
  76. #define CMD_PRECHARGE (2 << 19)
  77. #define CMD_REFRESH (1 << 19)
  78. #define CMD_EMR (0 << 19)
  79. #define CMD_READ (5 << 19)
  80. #define CMD_WRITE (4 << 19)
  81. #define SELECT_MR (0 << 16)
  82. #define SELECT_EMR (1 << 16)
  83. #define SELECT_EMR2 (2 << 16)
  84. #define SELECT_EMR3 (3 << 16)
  85. /* MR */
  86. #define DLL_RESET 0x00000100
  87. #define WRITE_RECOV_2 (1 << 9)
  88. #define WRITE_RECOV_3 (2 << 9)
  89. #define WRITE_RECOV_4 (3 << 9)
  90. #define WRITE_RECOV_5 (4 << 9)
  91. #define WRITE_RECOV_6 (5 << 9)
  92. #define BURST_LEN_4 0x00000002
  93. /* EMR */
  94. #define ODT_0_OHM 0x00000000
  95. #define ODT_50_OHM 0x00000044
  96. #define ODT_75_OHM 0x00000004
  97. #define ODT_150_OHM 0x00000040
  98. #define ODS_FULL 0x00000000
  99. #define ODS_REDUCED 0x00000002
  100. #define OCD_CALIB_DEF 0x00000380
  101. /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
  102. #define ODT_EB0R (0x80000000 >> 8)
  103. #define ODT_EB0W (0x80000000 >> 7)
  104. #define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
  105. #define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
  106. #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
  107. /* Defines for the Read Cycle Delay test */
  108. #define NUMMEMTESTS 8
  109. #define NUMMEMWORDS 8
  110. #define NUMLOOPS 64 /* memory test loops */
  111. /*
  112. * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  113. * region. Right now the cache should still be disabled in U-Boot because of the
  114. * EMAC driver, that need it's buffer descriptor to be located in non cached
  115. * memory.
  116. *
  117. * If at some time this restriction doesn't apply anymore, just define
  118. * CONFIG_4xx_DCACHE in the board config file and this code should setup
  119. * everything correctly.
  120. */
  121. #ifdef CONFIG_4xx_DCACHE
  122. #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
  123. #else
  124. #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
  125. #endif
  126. /*
  127. * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
  128. * To support such configurations, we "only" map the first 2GB via the TLB's. We
  129. * need some free virtual address space for the remaining peripherals like, SoC
  130. * devices, FLASH etc.
  131. *
  132. * Note that ECC is currently not supported on configurations with more than 2GB
  133. * SDRAM. This is because we only map the first 2GB on such systems, and therefore
  134. * the ECC parity byte of the remaining area can't be written.
  135. */
  136. #ifndef CONFIG_MAX_MEM_MAPPED
  137. #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
  138. #endif
  139. /*
  140. * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  141. */
  142. void __spd_ddr_init_hang (void)
  143. {
  144. hang ();
  145. }
  146. void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
  147. /*
  148. * To provide an interface for board specific config values in this common
  149. * DDR setup code, we implement he "weak" default functions here. They return
  150. * the default value back to the caller.
  151. *
  152. * Please see include/configs/yucca.h for an example fora board specific
  153. * implementation.
  154. */
  155. u32 __ddr_wrdtr(u32 default_val)
  156. {
  157. return default_val;
  158. }
  159. u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
  160. u32 __ddr_clktr(u32 default_val)
  161. {
  162. return default_val;
  163. }
  164. u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
  165. /* Private Structure Definitions */
  166. /* enum only to ease code for cas latency setting */
  167. typedef enum ddr_cas_id {
  168. DDR_CAS_2 = 20,
  169. DDR_CAS_2_5 = 25,
  170. DDR_CAS_3 = 30,
  171. DDR_CAS_4 = 40,
  172. DDR_CAS_5 = 50
  173. } ddr_cas_id_t;
  174. /*-----------------------------------------------------------------------------+
  175. * Prototypes
  176. *-----------------------------------------------------------------------------*/
  177. static phys_size_t sdram_memsize(void);
  178. static void get_spd_info(unsigned long *dimm_populated,
  179. unsigned char *iic0_dimm_addr,
  180. unsigned long num_dimm_banks);
  181. static void check_mem_type(unsigned long *dimm_populated,
  182. unsigned char *iic0_dimm_addr,
  183. unsigned long num_dimm_banks);
  184. static void check_frequency(unsigned long *dimm_populated,
  185. unsigned char *iic0_dimm_addr,
  186. unsigned long num_dimm_banks);
  187. static void check_rank_number(unsigned long *dimm_populated,
  188. unsigned char *iic0_dimm_addr,
  189. unsigned long num_dimm_banks);
  190. static void check_voltage_type(unsigned long *dimm_populated,
  191. unsigned char *iic0_dimm_addr,
  192. unsigned long num_dimm_banks);
  193. static void program_memory_queue(unsigned long *dimm_populated,
  194. unsigned char *iic0_dimm_addr,
  195. unsigned long num_dimm_banks);
  196. static void program_codt(unsigned long *dimm_populated,
  197. unsigned char *iic0_dimm_addr,
  198. unsigned long num_dimm_banks);
  199. static void program_mode(unsigned long *dimm_populated,
  200. unsigned char *iic0_dimm_addr,
  201. unsigned long num_dimm_banks,
  202. ddr_cas_id_t *selected_cas,
  203. int *write_recovery);
  204. static void program_tr(unsigned long *dimm_populated,
  205. unsigned char *iic0_dimm_addr,
  206. unsigned long num_dimm_banks);
  207. static void program_rtr(unsigned long *dimm_populated,
  208. unsigned char *iic0_dimm_addr,
  209. unsigned long num_dimm_banks);
  210. static void program_bxcf(unsigned long *dimm_populated,
  211. unsigned char *iic0_dimm_addr,
  212. unsigned long num_dimm_banks);
  213. static void program_copt1(unsigned long *dimm_populated,
  214. unsigned char *iic0_dimm_addr,
  215. unsigned long num_dimm_banks);
  216. static void program_initplr(unsigned long *dimm_populated,
  217. unsigned char *iic0_dimm_addr,
  218. unsigned long num_dimm_banks,
  219. ddr_cas_id_t selected_cas,
  220. int write_recovery);
  221. static unsigned long is_ecc_enabled(void);
  222. #ifdef CONFIG_DDR_ECC
  223. static void program_ecc(unsigned long *dimm_populated,
  224. unsigned char *iic0_dimm_addr,
  225. unsigned long num_dimm_banks,
  226. unsigned long tlb_word2_i_value);
  227. static void program_ecc_addr(unsigned long start_address,
  228. unsigned long num_bytes,
  229. unsigned long tlb_word2_i_value);
  230. #endif
  231. #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  232. static void program_DQS_calibration(unsigned long *dimm_populated,
  233. unsigned char *iic0_dimm_addr,
  234. unsigned long num_dimm_banks);
  235. #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
  236. static void test(void);
  237. #else
  238. static void DQS_calibration_process(void);
  239. #endif
  240. #endif
  241. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
  242. void dcbz_area(u32 start_address, u32 num_bytes);
  243. static unsigned char spd_read(uchar chip, uint addr)
  244. {
  245. unsigned char data[2];
  246. if (i2c_probe(chip) == 0)
  247. if (i2c_read(chip, addr, 1, data, 1) == 0)
  248. return data[0];
  249. return 0;
  250. }
  251. /*-----------------------------------------------------------------------------+
  252. * sdram_memsize
  253. *-----------------------------------------------------------------------------*/
  254. static phys_size_t sdram_memsize(void)
  255. {
  256. phys_size_t mem_size;
  257. unsigned long mcopt2;
  258. unsigned long mcstat;
  259. unsigned long mb0cf;
  260. unsigned long sdsz;
  261. unsigned long i;
  262. mem_size = 0;
  263. mfsdram(SDRAM_MCOPT2, mcopt2);
  264. mfsdram(SDRAM_MCSTAT, mcstat);
  265. /* DDR controller must be enabled and not in self-refresh. */
  266. /* Otherwise memsize is zero. */
  267. if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
  268. && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
  269. && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
  270. == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
  271. for (i = 0; i < MAXBXCF; i++) {
  272. mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
  273. /* Banks enabled */
  274. if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
  275. sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
  276. switch(sdsz) {
  277. case SDRAM_RXBAS_SDSZ_8:
  278. mem_size+=8;
  279. break;
  280. case SDRAM_RXBAS_SDSZ_16:
  281. mem_size+=16;
  282. break;
  283. case SDRAM_RXBAS_SDSZ_32:
  284. mem_size+=32;
  285. break;
  286. case SDRAM_RXBAS_SDSZ_64:
  287. mem_size+=64;
  288. break;
  289. case SDRAM_RXBAS_SDSZ_128:
  290. mem_size+=128;
  291. break;
  292. case SDRAM_RXBAS_SDSZ_256:
  293. mem_size+=256;
  294. break;
  295. case SDRAM_RXBAS_SDSZ_512:
  296. mem_size+=512;
  297. break;
  298. case SDRAM_RXBAS_SDSZ_1024:
  299. mem_size+=1024;
  300. break;
  301. case SDRAM_RXBAS_SDSZ_2048:
  302. mem_size+=2048;
  303. break;
  304. case SDRAM_RXBAS_SDSZ_4096:
  305. mem_size+=4096;
  306. break;
  307. default:
  308. printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
  309. , sdsz);
  310. mem_size=0;
  311. break;
  312. }
  313. }
  314. }
  315. }
  316. return mem_size << 20;
  317. }
  318. /*-----------------------------------------------------------------------------+
  319. * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
  320. * Note: This routine runs from flash with a stack set up in the chip's
  321. * sram space. It is important that the routine does not require .sbss, .bss or
  322. * .data sections. It also cannot call routines that require these sections.
  323. *-----------------------------------------------------------------------------*/
  324. /*-----------------------------------------------------------------------------
  325. * Function: initdram
  326. * Description: Configures SDRAM memory banks for DDR operation.
  327. * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
  328. * via the IIC bus and then configures the DDR SDRAM memory
  329. * banks appropriately. If Auto Memory Configuration is
  330. * not used, it is assumed that no DIMM is plugged
  331. *-----------------------------------------------------------------------------*/
  332. phys_size_t initdram(int board_type)
  333. {
  334. unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
  335. unsigned char spd0[MAX_SPD_BYTES];
  336. unsigned char spd1[MAX_SPD_BYTES];
  337. unsigned char *dimm_spd[MAXDIMMS];
  338. unsigned long dimm_populated[MAXDIMMS];
  339. unsigned long num_dimm_banks; /* on board dimm banks */
  340. unsigned long val;
  341. ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
  342. int write_recovery;
  343. phys_size_t dram_size = 0;
  344. num_dimm_banks = sizeof(iic0_dimm_addr);
  345. /*------------------------------------------------------------------
  346. * Set up an array of SPD matrixes.
  347. *-----------------------------------------------------------------*/
  348. dimm_spd[0] = spd0;
  349. dimm_spd[1] = spd1;
  350. /*------------------------------------------------------------------
  351. * Reset the DDR-SDRAM controller.
  352. *-----------------------------------------------------------------*/
  353. mtsdr(SDR0_SRST, (0x80000000 >> 10));
  354. mtsdr(SDR0_SRST, 0x00000000);
  355. /*
  356. * Make sure I2C controller is initialized
  357. * before continuing.
  358. */
  359. /* switch to correct I2C bus */
  360. I2C_SET_BUS(CFG_SPD_BUS_NUM);
  361. i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
  362. /*------------------------------------------------------------------
  363. * Clear out the serial presence detect buffers.
  364. * Perform IIC reads from the dimm. Fill in the spds.
  365. * Check to see if the dimm slots are populated
  366. *-----------------------------------------------------------------*/
  367. get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  368. /*------------------------------------------------------------------
  369. * Check the memory type for the dimms plugged.
  370. *-----------------------------------------------------------------*/
  371. check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  372. /*------------------------------------------------------------------
  373. * Check the frequency supported for the dimms plugged.
  374. *-----------------------------------------------------------------*/
  375. check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  376. /*------------------------------------------------------------------
  377. * Check the total rank number.
  378. *-----------------------------------------------------------------*/
  379. check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  380. /*------------------------------------------------------------------
  381. * Check the voltage type for the dimms plugged.
  382. *-----------------------------------------------------------------*/
  383. check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  384. /*------------------------------------------------------------------
  385. * Program SDRAM controller options 2 register
  386. * Except Enabling of the memory controller.
  387. *-----------------------------------------------------------------*/
  388. mfsdram(SDRAM_MCOPT2, val);
  389. mtsdram(SDRAM_MCOPT2,
  390. (val &
  391. ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
  392. SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
  393. SDRAM_MCOPT2_ISIE_MASK))
  394. | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
  395. SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
  396. SDRAM_MCOPT2_ISIE_ENABLE));
  397. /*------------------------------------------------------------------
  398. * Program SDRAM controller options 1 register
  399. * Note: Does not enable the memory controller.
  400. *-----------------------------------------------------------------*/
  401. program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  402. /*------------------------------------------------------------------
  403. * Set the SDRAM Controller On Die Termination Register
  404. *-----------------------------------------------------------------*/
  405. program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  406. /*------------------------------------------------------------------
  407. * Program SDRAM refresh register.
  408. *-----------------------------------------------------------------*/
  409. program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  410. /*------------------------------------------------------------------
  411. * Program SDRAM mode register.
  412. *-----------------------------------------------------------------*/
  413. program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
  414. &selected_cas, &write_recovery);
  415. /*------------------------------------------------------------------
  416. * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
  417. *-----------------------------------------------------------------*/
  418. mfsdram(SDRAM_WRDTR, val);
  419. mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
  420. ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
  421. /*------------------------------------------------------------------
  422. * Set the SDRAM Clock Timing Register
  423. *-----------------------------------------------------------------*/
  424. mfsdram(SDRAM_CLKTR, val);
  425. mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
  426. ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
  427. /*------------------------------------------------------------------
  428. * Program the BxCF registers.
  429. *-----------------------------------------------------------------*/
  430. program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  431. /*------------------------------------------------------------------
  432. * Program SDRAM timing registers.
  433. *-----------------------------------------------------------------*/
  434. program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  435. /*------------------------------------------------------------------
  436. * Set the Extended Mode register
  437. *-----------------------------------------------------------------*/
  438. mfsdram(SDRAM_MEMODE, val);
  439. mtsdram(SDRAM_MEMODE,
  440. (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
  441. SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
  442. (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
  443. | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
  444. /*------------------------------------------------------------------
  445. * Program Initialization preload registers.
  446. *-----------------------------------------------------------------*/
  447. program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
  448. selected_cas, write_recovery);
  449. /*------------------------------------------------------------------
  450. * Delay to ensure 200usec have elapsed since reset.
  451. *-----------------------------------------------------------------*/
  452. udelay(400);
  453. /*------------------------------------------------------------------
  454. * Set the memory queue core base addr.
  455. *-----------------------------------------------------------------*/
  456. program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  457. /*------------------------------------------------------------------
  458. * Program SDRAM controller options 2 register
  459. * Enable the memory controller.
  460. *-----------------------------------------------------------------*/
  461. mfsdram(SDRAM_MCOPT2, val);
  462. mtsdram(SDRAM_MCOPT2,
  463. (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
  464. SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
  465. SDRAM_MCOPT2_IPTR_EXECUTE);
  466. /*------------------------------------------------------------------
  467. * Wait for IPTR_EXECUTE init sequence to complete.
  468. *-----------------------------------------------------------------*/
  469. do {
  470. mfsdram(SDRAM_MCSTAT, val);
  471. } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
  472. /* enable the controller only after init sequence completes */
  473. mfsdram(SDRAM_MCOPT2, val);
  474. mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
  475. /* Make sure delay-line calibration is done before proceeding */
  476. do {
  477. mfsdram(SDRAM_DLCR, val);
  478. } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
  479. /* get installed memory size */
  480. dram_size = sdram_memsize();
  481. /*
  482. * Limit size to 2GB
  483. */
  484. if (dram_size > CONFIG_MAX_MEM_MAPPED)
  485. dram_size = CONFIG_MAX_MEM_MAPPED;
  486. /* and program tlb entries for this size (dynamic) */
  487. /*
  488. * Program TLB entries with caches enabled, for best performace
  489. * while auto-calibrating and ECC generation
  490. */
  491. program_tlb(0, 0, dram_size, 0);
  492. /*------------------------------------------------------------------
  493. * DQS calibration.
  494. *-----------------------------------------------------------------*/
  495. #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  496. DQS_autocalibration();
  497. #else
  498. program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
  499. #endif
  500. #ifdef CONFIG_DDR_ECC
  501. /*------------------------------------------------------------------
  502. * If ecc is enabled, initialize the parity bits.
  503. *-----------------------------------------------------------------*/
  504. program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
  505. #endif
  506. /*
  507. * Now after initialization (auto-calibration and ECC generation)
  508. * remove the TLB entries with caches enabled and program again with
  509. * desired cache functionality
  510. */
  511. remove_tlb(0, dram_size);
  512. program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
  513. ppc4xx_ibm_ddr2_register_dump();
  514. /*
  515. * Clear potential errors resulting from auto-calibration.
  516. * If not done, then we could get an interrupt later on when
  517. * exceptions are enabled.
  518. */
  519. set_mcsr(get_mcsr());
  520. return sdram_memsize();
  521. }
  522. static void get_spd_info(unsigned long *dimm_populated,
  523. unsigned char *iic0_dimm_addr,
  524. unsigned long num_dimm_banks)
  525. {
  526. unsigned long dimm_num;
  527. unsigned long dimm_found;
  528. unsigned char num_of_bytes;
  529. unsigned char total_size;
  530. dimm_found = FALSE;
  531. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  532. num_of_bytes = 0;
  533. total_size = 0;
  534. num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
  535. debug("\nspd_read(0x%x) returned %d\n",
  536. iic0_dimm_addr[dimm_num], num_of_bytes);
  537. total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
  538. debug("spd_read(0x%x) returned %d\n",
  539. iic0_dimm_addr[dimm_num], total_size);
  540. if ((num_of_bytes != 0) && (total_size != 0)) {
  541. dimm_populated[dimm_num] = TRUE;
  542. dimm_found = TRUE;
  543. debug("DIMM slot %lu: populated\n", dimm_num);
  544. } else {
  545. dimm_populated[dimm_num] = FALSE;
  546. debug("DIMM slot %lu: Not populated\n", dimm_num);
  547. }
  548. }
  549. if (dimm_found == FALSE) {
  550. printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
  551. spd_ddr_init_hang ();
  552. }
  553. }
  554. void board_add_ram_info(int use_default)
  555. {
  556. PPC4xx_SYS_INFO board_cfg;
  557. u32 val;
  558. if (is_ecc_enabled())
  559. puts(" (ECC");
  560. else
  561. puts(" (ECC not");
  562. get_sys_info(&board_cfg);
  563. mfsdr(SDR0_DDR0, val);
  564. val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
  565. printf(" enabled, %d MHz", (val * 2) / 1000000);
  566. mfsdram(SDRAM_MMODE, val);
  567. val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
  568. printf(", CL%d)", val);
  569. }
  570. /*------------------------------------------------------------------
  571. * For the memory DIMMs installed, this routine verifies that they
  572. * really are DDR specific DIMMs.
  573. *-----------------------------------------------------------------*/
  574. static void check_mem_type(unsigned long *dimm_populated,
  575. unsigned char *iic0_dimm_addr,
  576. unsigned long num_dimm_banks)
  577. {
  578. unsigned long dimm_num;
  579. unsigned long dimm_type;
  580. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  581. if (dimm_populated[dimm_num] == TRUE) {
  582. dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
  583. switch (dimm_type) {
  584. case 1:
  585. printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
  586. "slot %d.\n", (unsigned int)dimm_num);
  587. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  588. printf("Replace the DIMM module with a supported DIMM.\n\n");
  589. spd_ddr_init_hang ();
  590. break;
  591. case 2:
  592. printf("ERROR: EDO DIMM detected in slot %d.\n",
  593. (unsigned int)dimm_num);
  594. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  595. printf("Replace the DIMM module with a supported DIMM.\n\n");
  596. spd_ddr_init_hang ();
  597. break;
  598. case 3:
  599. printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
  600. (unsigned int)dimm_num);
  601. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  602. printf("Replace the DIMM module with a supported DIMM.\n\n");
  603. spd_ddr_init_hang ();
  604. break;
  605. case 4:
  606. printf("ERROR: SDRAM DIMM detected in slot %d.\n",
  607. (unsigned int)dimm_num);
  608. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  609. printf("Replace the DIMM module with a supported DIMM.\n\n");
  610. spd_ddr_init_hang ();
  611. break;
  612. case 5:
  613. printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
  614. (unsigned int)dimm_num);
  615. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  616. printf("Replace the DIMM module with a supported DIMM.\n\n");
  617. spd_ddr_init_hang ();
  618. break;
  619. case 6:
  620. printf("ERROR: SGRAM DIMM detected in slot %d.\n",
  621. (unsigned int)dimm_num);
  622. printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
  623. printf("Replace the DIMM module with a supported DIMM.\n\n");
  624. spd_ddr_init_hang ();
  625. break;
  626. case 7:
  627. debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
  628. dimm_populated[dimm_num] = SDRAM_DDR1;
  629. break;
  630. case 8:
  631. debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
  632. dimm_populated[dimm_num] = SDRAM_DDR2;
  633. break;
  634. default:
  635. printf("ERROR: Unknown DIMM detected in slot %d.\n",
  636. (unsigned int)dimm_num);
  637. printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
  638. printf("Replace the DIMM module with a supported DIMM.\n\n");
  639. spd_ddr_init_hang ();
  640. break;
  641. }
  642. }
  643. }
  644. for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
  645. if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
  646. && (dimm_populated[dimm_num] != SDRAM_NONE)
  647. && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
  648. printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
  649. spd_ddr_init_hang ();
  650. }
  651. }
  652. }
  653. /*------------------------------------------------------------------
  654. * For the memory DIMMs installed, this routine verifies that
  655. * frequency previously calculated is supported.
  656. *-----------------------------------------------------------------*/
  657. static void check_frequency(unsigned long *dimm_populated,
  658. unsigned char *iic0_dimm_addr,
  659. unsigned long num_dimm_banks)
  660. {
  661. unsigned long dimm_num;
  662. unsigned long tcyc_reg;
  663. unsigned long cycle_time;
  664. unsigned long calc_cycle_time;
  665. unsigned long sdram_freq;
  666. unsigned long sdr_ddrpll;
  667. PPC4xx_SYS_INFO board_cfg;
  668. /*------------------------------------------------------------------
  669. * Get the board configuration info.
  670. *-----------------------------------------------------------------*/
  671. get_sys_info(&board_cfg);
  672. mfsdr(SDR0_DDR0, sdr_ddrpll);
  673. sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
  674. /*
  675. * calc_cycle_time is calculated from DDR frequency set by board/chip
  676. * and is expressed in multiple of 10 picoseconds
  677. * to match the way DIMM cycle time is calculated below.
  678. */
  679. calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
  680. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  681. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  682. tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
  683. /*
  684. * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
  685. * the higher order nibble (bits 4-7) designates the cycle time
  686. * to a granularity of 1ns;
  687. * the value presented by the lower order nibble (bits 0-3)
  688. * has a granularity of .1ns and is added to the value designated
  689. * by the higher nibble. In addition, four lines of the lower order
  690. * nibble are assigned to support +.25,+.33, +.66 and +.75.
  691. */
  692. /* Convert from hex to decimal */
  693. if ((tcyc_reg & 0x0F) == 0x0D)
  694. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
  695. else if ((tcyc_reg & 0x0F) == 0x0C)
  696. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
  697. else if ((tcyc_reg & 0x0F) == 0x0B)
  698. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
  699. else if ((tcyc_reg & 0x0F) == 0x0A)
  700. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
  701. else
  702. cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
  703. ((tcyc_reg & 0x0F)*10);
  704. debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
  705. if (cycle_time > (calc_cycle_time + 10)) {
  706. /*
  707. * the provided sdram cycle_time is too small
  708. * for the available DIMM cycle_time.
  709. * The additionnal 100ps is here to accept a small incertainty.
  710. */
  711. printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
  712. "slot %d \n while calculated cycle time is %d ps.\n",
  713. (unsigned int)(cycle_time*10),
  714. (unsigned int)dimm_num,
  715. (unsigned int)(calc_cycle_time*10));
  716. printf("Replace the DIMM, or change DDR frequency via "
  717. "strapping bits.\n\n");
  718. spd_ddr_init_hang ();
  719. }
  720. }
  721. }
  722. }
  723. /*------------------------------------------------------------------
  724. * For the memory DIMMs installed, this routine verifies two
  725. * ranks/banks maximum are availables.
  726. *-----------------------------------------------------------------*/
  727. static void check_rank_number(unsigned long *dimm_populated,
  728. unsigned char *iic0_dimm_addr,
  729. unsigned long num_dimm_banks)
  730. {
  731. unsigned long dimm_num;
  732. unsigned long dimm_rank;
  733. unsigned long total_rank = 0;
  734. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  735. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  736. dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
  737. if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
  738. dimm_rank = (dimm_rank & 0x0F) +1;
  739. else
  740. dimm_rank = dimm_rank & 0x0F;
  741. if (dimm_rank > MAXRANKS) {
  742. printf("ERROR: DRAM DIMM detected with %lu ranks in "
  743. "slot %lu is not supported.\n", dimm_rank, dimm_num);
  744. printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
  745. printf("Replace the DIMM module with a supported DIMM.\n\n");
  746. spd_ddr_init_hang ();
  747. } else
  748. total_rank += dimm_rank;
  749. }
  750. if (total_rank > MAXRANKS) {
  751. printf("ERROR: DRAM DIMM detected with a total of %d ranks "
  752. "for all slots.\n", (unsigned int)total_rank);
  753. printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
  754. printf("Remove one of the DIMM modules.\n\n");
  755. spd_ddr_init_hang ();
  756. }
  757. }
  758. }
  759. /*------------------------------------------------------------------
  760. * only support 2.5V modules.
  761. * This routine verifies this.
  762. *-----------------------------------------------------------------*/
  763. static void check_voltage_type(unsigned long *dimm_populated,
  764. unsigned char *iic0_dimm_addr,
  765. unsigned long num_dimm_banks)
  766. {
  767. unsigned long dimm_num;
  768. unsigned long voltage_type;
  769. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  770. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  771. voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
  772. switch (voltage_type) {
  773. case 0x00:
  774. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  775. printf("This DIMM is 5.0 Volt/TTL.\n");
  776. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  777. (unsigned int)dimm_num);
  778. spd_ddr_init_hang ();
  779. break;
  780. case 0x01:
  781. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  782. printf("This DIMM is LVTTL.\n");
  783. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  784. (unsigned int)dimm_num);
  785. spd_ddr_init_hang ();
  786. break;
  787. case 0x02:
  788. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  789. printf("This DIMM is 1.5 Volt.\n");
  790. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  791. (unsigned int)dimm_num);
  792. spd_ddr_init_hang ();
  793. break;
  794. case 0x03:
  795. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  796. printf("This DIMM is 3.3 Volt/TTL.\n");
  797. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  798. (unsigned int)dimm_num);
  799. spd_ddr_init_hang ();
  800. break;
  801. case 0x04:
  802. /* 2.5 Voltage only for DDR1 */
  803. break;
  804. case 0x05:
  805. /* 1.8 Voltage only for DDR2 */
  806. break;
  807. default:
  808. printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
  809. printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
  810. (unsigned int)dimm_num);
  811. spd_ddr_init_hang ();
  812. break;
  813. }
  814. }
  815. }
  816. }
  817. /*-----------------------------------------------------------------------------+
  818. * program_copt1.
  819. *-----------------------------------------------------------------------------*/
  820. static void program_copt1(unsigned long *dimm_populated,
  821. unsigned char *iic0_dimm_addr,
  822. unsigned long num_dimm_banks)
  823. {
  824. unsigned long dimm_num;
  825. unsigned long mcopt1;
  826. unsigned long ecc_enabled;
  827. unsigned long ecc = 0;
  828. unsigned long data_width = 0;
  829. unsigned long dimm_32bit;
  830. unsigned long dimm_64bit;
  831. unsigned long registered = 0;
  832. unsigned long attribute = 0;
  833. unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
  834. unsigned long bankcount;
  835. unsigned long ddrtype;
  836. unsigned long val;
  837. #ifdef CONFIG_DDR_ECC
  838. ecc_enabled = TRUE;
  839. #else
  840. ecc_enabled = FALSE;
  841. #endif
  842. dimm_32bit = FALSE;
  843. dimm_64bit = FALSE;
  844. buf0 = FALSE;
  845. buf1 = FALSE;
  846. /*------------------------------------------------------------------
  847. * Set memory controller options reg 1, SDRAM_MCOPT1.
  848. *-----------------------------------------------------------------*/
  849. mfsdram(SDRAM_MCOPT1, val);
  850. mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
  851. SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
  852. SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
  853. SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
  854. SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
  855. SDRAM_MCOPT1_DREF_MASK);
  856. mcopt1 |= SDRAM_MCOPT1_QDEP;
  857. mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
  858. mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
  859. mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
  860. mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
  861. mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
  862. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  863. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  864. /* test ecc support */
  865. ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
  866. if (ecc != 0x02) /* ecc not supported */
  867. ecc_enabled = FALSE;
  868. /* test bank count */
  869. bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
  870. if (bankcount == 0x04) /* bank count = 4 */
  871. mcopt1 |= SDRAM_MCOPT1_4_BANKS;
  872. else /* bank count = 8 */
  873. mcopt1 |= SDRAM_MCOPT1_8_BANKS;
  874. /* test DDR type */
  875. ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
  876. /* test for buffered/unbuffered, registered, differential clocks */
  877. registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
  878. attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
  879. /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
  880. if (dimm_num == 0) {
  881. if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
  882. mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
  883. if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
  884. mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
  885. if (registered == 1) { /* DDR2 always buffered */
  886. /* TODO: what about above comments ? */
  887. mcopt1 |= SDRAM_MCOPT1_RDEN;
  888. buf0 = TRUE;
  889. } else {
  890. /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
  891. if ((attribute & 0x02) == 0x00) {
  892. /* buffered not supported */
  893. buf0 = FALSE;
  894. } else {
  895. mcopt1 |= SDRAM_MCOPT1_RDEN;
  896. buf0 = TRUE;
  897. }
  898. }
  899. }
  900. else if (dimm_num == 1) {
  901. if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
  902. mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
  903. if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
  904. mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
  905. if (registered == 1) {
  906. /* DDR2 always buffered */
  907. mcopt1 |= SDRAM_MCOPT1_RDEN;
  908. buf1 = TRUE;
  909. } else {
  910. if ((attribute & 0x02) == 0x00) {
  911. /* buffered not supported */
  912. buf1 = FALSE;
  913. } else {
  914. mcopt1 |= SDRAM_MCOPT1_RDEN;
  915. buf1 = TRUE;
  916. }
  917. }
  918. }
  919. /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
  920. data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
  921. (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
  922. switch (data_width) {
  923. case 72:
  924. case 64:
  925. dimm_64bit = TRUE;
  926. break;
  927. case 40:
  928. case 32:
  929. dimm_32bit = TRUE;
  930. break;
  931. default:
  932. printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
  933. data_width);
  934. printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
  935. break;
  936. }
  937. }
  938. }
  939. /* verify matching properties */
  940. if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
  941. if (buf0 != buf1) {
  942. printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
  943. spd_ddr_init_hang ();
  944. }
  945. }
  946. if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
  947. printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
  948. spd_ddr_init_hang ();
  949. }
  950. else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
  951. mcopt1 |= SDRAM_MCOPT1_DMWD_64;
  952. } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
  953. mcopt1 |= SDRAM_MCOPT1_DMWD_32;
  954. } else {
  955. printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
  956. spd_ddr_init_hang ();
  957. }
  958. if (ecc_enabled == TRUE)
  959. mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
  960. else
  961. mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
  962. mtsdram(SDRAM_MCOPT1, mcopt1);
  963. }
  964. /*-----------------------------------------------------------------------------+
  965. * program_codt.
  966. *-----------------------------------------------------------------------------*/
  967. static void program_codt(unsigned long *dimm_populated,
  968. unsigned char *iic0_dimm_addr,
  969. unsigned long num_dimm_banks)
  970. {
  971. unsigned long codt;
  972. unsigned long modt0 = 0;
  973. unsigned long modt1 = 0;
  974. unsigned long modt2 = 0;
  975. unsigned long modt3 = 0;
  976. unsigned char dimm_num;
  977. unsigned char dimm_rank;
  978. unsigned char total_rank = 0;
  979. unsigned char total_dimm = 0;
  980. unsigned char dimm_type = 0;
  981. unsigned char firstSlot = 0;
  982. /*------------------------------------------------------------------
  983. * Set the SDRAM Controller On Die Termination Register
  984. *-----------------------------------------------------------------*/
  985. mfsdram(SDRAM_CODT, codt);
  986. codt |= (SDRAM_CODT_IO_NMODE
  987. & (~SDRAM_CODT_DQS_SINGLE_END
  988. & ~SDRAM_CODT_CKSE_SINGLE_END
  989. & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
  990. & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
  991. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  992. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  993. dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
  994. if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
  995. dimm_rank = (dimm_rank & 0x0F) + 1;
  996. dimm_type = SDRAM_DDR2;
  997. } else {
  998. dimm_rank = dimm_rank & 0x0F;
  999. dimm_type = SDRAM_DDR1;
  1000. }
  1001. total_rank += dimm_rank;
  1002. total_dimm++;
  1003. if ((dimm_num == 0) && (total_dimm == 1))
  1004. firstSlot = TRUE;
  1005. else
  1006. firstSlot = FALSE;
  1007. }
  1008. }
  1009. if (dimm_type == SDRAM_DDR2) {
  1010. codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
  1011. if ((total_dimm == 1) && (firstSlot == TRUE)) {
  1012. if (total_rank == 1) { /* PUUU */
  1013. codt |= CALC_ODT_R(0);
  1014. modt0 = CALC_ODT_W(0);
  1015. modt1 = 0x00000000;
  1016. modt2 = 0x00000000;
  1017. modt3 = 0x00000000;
  1018. }
  1019. if (total_rank == 2) { /* PPUU */
  1020. codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
  1021. modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
  1022. modt1 = 0x00000000;
  1023. modt2 = 0x00000000;
  1024. modt3 = 0x00000000;
  1025. }
  1026. } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
  1027. if (total_rank == 1) { /* UUPU */
  1028. codt |= CALC_ODT_R(2);
  1029. modt0 = 0x00000000;
  1030. modt1 = 0x00000000;
  1031. modt2 = CALC_ODT_W(2);
  1032. modt3 = 0x00000000;
  1033. }
  1034. if (total_rank == 2) { /* UUPP */
  1035. codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
  1036. modt0 = 0x00000000;
  1037. modt1 = 0x00000000;
  1038. modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
  1039. modt3 = 0x00000000;
  1040. }
  1041. }
  1042. if (total_dimm == 2) {
  1043. if (total_rank == 2) { /* PUPU */
  1044. codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
  1045. modt0 = CALC_ODT_RW(2);
  1046. modt1 = 0x00000000;
  1047. modt2 = CALC_ODT_RW(0);
  1048. modt3 = 0x00000000;
  1049. }
  1050. if (total_rank == 4) { /* PPPP */
  1051. codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
  1052. CALC_ODT_R(2) | CALC_ODT_R(3);
  1053. modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
  1054. modt1 = 0x00000000;
  1055. modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
  1056. modt3 = 0x00000000;
  1057. }
  1058. }
  1059. } else {
  1060. codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
  1061. modt0 = 0x00000000;
  1062. modt1 = 0x00000000;
  1063. modt2 = 0x00000000;
  1064. modt3 = 0x00000000;
  1065. if (total_dimm == 1) {
  1066. if (total_rank == 1)
  1067. codt |= 0x00800000;
  1068. if (total_rank == 2)
  1069. codt |= 0x02800000;
  1070. }
  1071. if (total_dimm == 2) {
  1072. if (total_rank == 2)
  1073. codt |= 0x08800000;
  1074. if (total_rank == 4)
  1075. codt |= 0x2a800000;
  1076. }
  1077. }
  1078. debug("nb of dimm %d\n", total_dimm);
  1079. debug("nb of rank %d\n", total_rank);
  1080. if (total_dimm == 1)
  1081. debug("dimm in slot %d\n", firstSlot);
  1082. mtsdram(SDRAM_CODT, codt);
  1083. mtsdram(SDRAM_MODT0, modt0);
  1084. mtsdram(SDRAM_MODT1, modt1);
  1085. mtsdram(SDRAM_MODT2, modt2);
  1086. mtsdram(SDRAM_MODT3, modt3);
  1087. }
  1088. /*-----------------------------------------------------------------------------+
  1089. * program_initplr.
  1090. *-----------------------------------------------------------------------------*/
  1091. static void program_initplr(unsigned long *dimm_populated,
  1092. unsigned char *iic0_dimm_addr,
  1093. unsigned long num_dimm_banks,
  1094. ddr_cas_id_t selected_cas,
  1095. int write_recovery)
  1096. {
  1097. u32 cas = 0;
  1098. u32 odt = 0;
  1099. u32 ods = 0;
  1100. u32 mr;
  1101. u32 wr;
  1102. u32 emr;
  1103. u32 emr2;
  1104. u32 emr3;
  1105. int dimm_num;
  1106. int total_dimm = 0;
  1107. /******************************************************
  1108. ** Assumption: if more than one DIMM, all DIMMs are the same
  1109. ** as already checked in check_memory_type
  1110. ******************************************************/
  1111. if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
  1112. mtsdram(SDRAM_INITPLR0, 0x81B80000);
  1113. mtsdram(SDRAM_INITPLR1, 0x81900400);
  1114. mtsdram(SDRAM_INITPLR2, 0x81810000);
  1115. mtsdram(SDRAM_INITPLR3, 0xff800162);
  1116. mtsdram(SDRAM_INITPLR4, 0x81900400);
  1117. mtsdram(SDRAM_INITPLR5, 0x86080000);
  1118. mtsdram(SDRAM_INITPLR6, 0x86080000);
  1119. mtsdram(SDRAM_INITPLR7, 0x81000062);
  1120. } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
  1121. switch (selected_cas) {
  1122. case DDR_CAS_3:
  1123. cas = 3 << 4;
  1124. break;
  1125. case DDR_CAS_4:
  1126. cas = 4 << 4;
  1127. break;
  1128. case DDR_CAS_5:
  1129. cas = 5 << 4;
  1130. break;
  1131. default:
  1132. printf("ERROR: ucode error on selected_cas value %d", selected_cas);
  1133. spd_ddr_init_hang ();
  1134. break;
  1135. }
  1136. #if 0
  1137. /*
  1138. * ToDo - Still a problem with the write recovery:
  1139. * On the Corsair CM2X512-5400C4 module, setting write recovery
  1140. * in the INITPLR reg to the value calculated in program_mode()
  1141. * results in not correctly working DDR2 memory (crash after
  1142. * relocation).
  1143. *
  1144. * So for now, set the write recovery to 3. This seems to work
  1145. * on the Corair module too.
  1146. *
  1147. * 2007-03-01, sr
  1148. */
  1149. switch (write_recovery) {
  1150. case 3:
  1151. wr = WRITE_RECOV_3;
  1152. break;
  1153. case 4:
  1154. wr = WRITE_RECOV_4;
  1155. break;
  1156. case 5:
  1157. wr = WRITE_RECOV_5;
  1158. break;
  1159. case 6:
  1160. wr = WRITE_RECOV_6;
  1161. break;
  1162. default:
  1163. printf("ERROR: write recovery not support (%d)", write_recovery);
  1164. spd_ddr_init_hang ();
  1165. break;
  1166. }
  1167. #else
  1168. wr = WRITE_RECOV_3; /* test-only, see description above */
  1169. #endif
  1170. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
  1171. if (dimm_populated[dimm_num] != SDRAM_NONE)
  1172. total_dimm++;
  1173. if (total_dimm == 1) {
  1174. odt = ODT_150_OHM;
  1175. ods = ODS_FULL;
  1176. } else if (total_dimm == 2) {
  1177. odt = ODT_75_OHM;
  1178. ods = ODS_REDUCED;
  1179. } else {
  1180. printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
  1181. spd_ddr_init_hang ();
  1182. }
  1183. mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
  1184. emr = CMD_EMR | SELECT_EMR | odt | ods;
  1185. emr2 = CMD_EMR | SELECT_EMR2;
  1186. emr3 = CMD_EMR | SELECT_EMR3;
  1187. /* NOP - Wait 106 MemClk cycles */
  1188. mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
  1189. SDRAM_INITPLR_IMWT_ENCODE(106));
  1190. udelay(1000);
  1191. /* precharge 4 MemClk cycles */
  1192. mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
  1193. SDRAM_INITPLR_IMWT_ENCODE(4));
  1194. /* EMR2 - Wait tMRD (2 MemClk cycles) */
  1195. mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
  1196. SDRAM_INITPLR_IMWT_ENCODE(2));
  1197. /* EMR3 - Wait tMRD (2 MemClk cycles) */
  1198. mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
  1199. SDRAM_INITPLR_IMWT_ENCODE(2));
  1200. /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
  1201. mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
  1202. SDRAM_INITPLR_IMWT_ENCODE(2));
  1203. /* MR w/ DLL reset - 200 cycle wait for DLL reset */
  1204. mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
  1205. SDRAM_INITPLR_IMWT_ENCODE(200));
  1206. udelay(1000);
  1207. /* precharge 4 MemClk cycles */
  1208. mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
  1209. SDRAM_INITPLR_IMWT_ENCODE(4));
  1210. /* Refresh 25 MemClk cycles */
  1211. mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
  1212. SDRAM_INITPLR_IMWT_ENCODE(25));
  1213. /* Refresh 25 MemClk cycles */
  1214. mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
  1215. SDRAM_INITPLR_IMWT_ENCODE(25));
  1216. /* Refresh 25 MemClk cycles */
  1217. mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
  1218. SDRAM_INITPLR_IMWT_ENCODE(25));
  1219. /* Refresh 25 MemClk cycles */
  1220. mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
  1221. SDRAM_INITPLR_IMWT_ENCODE(25));
  1222. /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
  1223. mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
  1224. SDRAM_INITPLR_IMWT_ENCODE(2));
  1225. /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
  1226. mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
  1227. SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
  1228. /* EMR OCD Exit */
  1229. mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
  1230. SDRAM_INITPLR_IMWT_ENCODE(2));
  1231. } else {
  1232. printf("ERROR: ucode error as unknown DDR type in program_initplr");
  1233. spd_ddr_init_hang ();
  1234. }
  1235. }
  1236. /*------------------------------------------------------------------
  1237. * This routine programs the SDRAM_MMODE register.
  1238. * the selected_cas is an output parameter, that will be passed
  1239. * by caller to call the above program_initplr( )
  1240. *-----------------------------------------------------------------*/
  1241. static void program_mode(unsigned long *dimm_populated,
  1242. unsigned char *iic0_dimm_addr,
  1243. unsigned long num_dimm_banks,
  1244. ddr_cas_id_t *selected_cas,
  1245. int *write_recovery)
  1246. {
  1247. unsigned long dimm_num;
  1248. unsigned long sdram_ddr1;
  1249. unsigned long t_wr_ns;
  1250. unsigned long t_wr_clk;
  1251. unsigned long cas_bit;
  1252. unsigned long cas_index;
  1253. unsigned long sdram_freq;
  1254. unsigned long ddr_check;
  1255. unsigned long mmode;
  1256. unsigned long tcyc_reg;
  1257. unsigned long cycle_2_0_clk;
  1258. unsigned long cycle_2_5_clk;
  1259. unsigned long cycle_3_0_clk;
  1260. unsigned long cycle_4_0_clk;
  1261. unsigned long cycle_5_0_clk;
  1262. unsigned long max_2_0_tcyc_ns_x_100;
  1263. unsigned long max_2_5_tcyc_ns_x_100;
  1264. unsigned long max_3_0_tcyc_ns_x_100;
  1265. unsigned long max_4_0_tcyc_ns_x_100;
  1266. unsigned long max_5_0_tcyc_ns_x_100;
  1267. unsigned long cycle_time_ns_x_100[3];
  1268. PPC4xx_SYS_INFO board_cfg;
  1269. unsigned char cas_2_0_available;
  1270. unsigned char cas_2_5_available;
  1271. unsigned char cas_3_0_available;
  1272. unsigned char cas_4_0_available;
  1273. unsigned char cas_5_0_available;
  1274. unsigned long sdr_ddrpll;
  1275. /*------------------------------------------------------------------
  1276. * Get the board configuration info.
  1277. *-----------------------------------------------------------------*/
  1278. get_sys_info(&board_cfg);
  1279. mfsdr(SDR0_DDR0, sdr_ddrpll);
  1280. sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
  1281. debug("sdram_freq=%d\n", sdram_freq);
  1282. /*------------------------------------------------------------------
  1283. * Handle the timing. We need to find the worst case timing of all
  1284. * the dimm modules installed.
  1285. *-----------------------------------------------------------------*/
  1286. t_wr_ns = 0;
  1287. cas_2_0_available = TRUE;
  1288. cas_2_5_available = TRUE;
  1289. cas_3_0_available = TRUE;
  1290. cas_4_0_available = TRUE;
  1291. cas_5_0_available = TRUE;
  1292. max_2_0_tcyc_ns_x_100 = 10;
  1293. max_2_5_tcyc_ns_x_100 = 10;
  1294. max_3_0_tcyc_ns_x_100 = 10;
  1295. max_4_0_tcyc_ns_x_100 = 10;
  1296. max_5_0_tcyc_ns_x_100 = 10;
  1297. sdram_ddr1 = TRUE;
  1298. /* loop through all the DIMM slots on the board */
  1299. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1300. /* If a dimm is installed in a particular slot ... */
  1301. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1302. if (dimm_populated[dimm_num] == SDRAM_DDR1)
  1303. sdram_ddr1 = TRUE;
  1304. else
  1305. sdram_ddr1 = FALSE;
  1306. /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
  1307. cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
  1308. debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
  1309. /* For a particular DIMM, grab the three CAS values it supports */
  1310. for (cas_index = 0; cas_index < 3; cas_index++) {
  1311. switch (cas_index) {
  1312. case 0:
  1313. tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
  1314. break;
  1315. case 1:
  1316. tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
  1317. break;
  1318. default:
  1319. tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
  1320. break;
  1321. }
  1322. if ((tcyc_reg & 0x0F) >= 10) {
  1323. if ((tcyc_reg & 0x0F) == 0x0D) {
  1324. /* Convert from hex to decimal */
  1325. cycle_time_ns_x_100[cas_index] =
  1326. (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
  1327. } else {
  1328. printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
  1329. "in slot %d\n", (unsigned int)dimm_num);
  1330. spd_ddr_init_hang ();
  1331. }
  1332. } else {
  1333. /* Convert from hex to decimal */
  1334. cycle_time_ns_x_100[cas_index] =
  1335. (((tcyc_reg & 0xF0) >> 4) * 100) +
  1336. ((tcyc_reg & 0x0F)*10);
  1337. }
  1338. debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
  1339. cycle_time_ns_x_100[cas_index]);
  1340. }
  1341. /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
  1342. /* supported for a particular DIMM. */
  1343. cas_index = 0;
  1344. if (sdram_ddr1) {
  1345. /*
  1346. * DDR devices use the following bitmask for CAS latency:
  1347. * Bit 7 6 5 4 3 2 1 0
  1348. * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
  1349. */
  1350. if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
  1351. (cycle_time_ns_x_100[cas_index] != 0)) {
  1352. max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
  1353. cycle_time_ns_x_100[cas_index]);
  1354. cas_index++;
  1355. } else {
  1356. if (cas_index != 0)
  1357. cas_index++;
  1358. cas_4_0_available = FALSE;
  1359. }
  1360. if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
  1361. (cycle_time_ns_x_100[cas_index] != 0)) {
  1362. max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
  1363. cycle_time_ns_x_100[cas_index]);
  1364. cas_index++;
  1365. } else {
  1366. if (cas_index != 0)
  1367. cas_index++;
  1368. cas_3_0_available = FALSE;
  1369. }
  1370. if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
  1371. (cycle_time_ns_x_100[cas_index] != 0)) {
  1372. max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
  1373. cycle_time_ns_x_100[cas_index]);
  1374. cas_index++;
  1375. } else {
  1376. if (cas_index != 0)
  1377. cas_index++;
  1378. cas_2_5_available = FALSE;
  1379. }
  1380. if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
  1381. (cycle_time_ns_x_100[cas_index] != 0)) {
  1382. max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
  1383. cycle_time_ns_x_100[cas_index]);
  1384. cas_index++;
  1385. } else {
  1386. if (cas_index != 0)
  1387. cas_index++;
  1388. cas_2_0_available = FALSE;
  1389. }
  1390. } else {
  1391. /*
  1392. * DDR2 devices use the following bitmask for CAS latency:
  1393. * Bit 7 6 5 4 3 2 1 0
  1394. * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
  1395. */
  1396. if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
  1397. (cycle_time_ns_x_100[cas_index] != 0)) {
  1398. max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
  1399. cycle_time_ns_x_100[cas_index]);
  1400. cas_index++;
  1401. } else {
  1402. if (cas_index != 0)
  1403. cas_index++;
  1404. cas_5_0_available = FALSE;
  1405. }
  1406. if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
  1407. (cycle_time_ns_x_100[cas_index] != 0)) {
  1408. max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
  1409. cycle_time_ns_x_100[cas_index]);
  1410. cas_index++;
  1411. } else {
  1412. if (cas_index != 0)
  1413. cas_index++;
  1414. cas_4_0_available = FALSE;
  1415. }
  1416. if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
  1417. (cycle_time_ns_x_100[cas_index] != 0)) {
  1418. max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
  1419. cycle_time_ns_x_100[cas_index]);
  1420. cas_index++;
  1421. } else {
  1422. if (cas_index != 0)
  1423. cas_index++;
  1424. cas_3_0_available = FALSE;
  1425. }
  1426. }
  1427. }
  1428. }
  1429. /*------------------------------------------------------------------
  1430. * Set the SDRAM mode, SDRAM_MMODE
  1431. *-----------------------------------------------------------------*/
  1432. mfsdram(SDRAM_MMODE, mmode);
  1433. mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
  1434. /* add 10 here because of rounding problems */
  1435. cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
  1436. cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
  1437. cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
  1438. cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
  1439. cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
  1440. debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
  1441. debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
  1442. debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
  1443. if (sdram_ddr1 == TRUE) { /* DDR1 */
  1444. if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
  1445. mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
  1446. *selected_cas = DDR_CAS_2;
  1447. } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
  1448. mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
  1449. *selected_cas = DDR_CAS_2_5;
  1450. } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
  1451. mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
  1452. *selected_cas = DDR_CAS_3;
  1453. } else {
  1454. printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
  1455. printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
  1456. printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
  1457. spd_ddr_init_hang ();
  1458. }
  1459. } else { /* DDR2 */
  1460. debug("cas_3_0_available=%d\n", cas_3_0_available);
  1461. debug("cas_4_0_available=%d\n", cas_4_0_available);
  1462. debug("cas_5_0_available=%d\n", cas_5_0_available);
  1463. if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
  1464. mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
  1465. *selected_cas = DDR_CAS_3;
  1466. } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
  1467. mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
  1468. *selected_cas = DDR_CAS_4;
  1469. } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
  1470. mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
  1471. *selected_cas = DDR_CAS_5;
  1472. } else {
  1473. printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
  1474. printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
  1475. printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
  1476. printf("cas3=%d cas4=%d cas5=%d\n",
  1477. cas_3_0_available, cas_4_0_available, cas_5_0_available);
  1478. printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
  1479. sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
  1480. spd_ddr_init_hang ();
  1481. }
  1482. }
  1483. if (sdram_ddr1 == TRUE)
  1484. mmode |= SDRAM_MMODE_WR_DDR1;
  1485. else {
  1486. /* loop through all the DIMM slots on the board */
  1487. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1488. /* If a dimm is installed in a particular slot ... */
  1489. if (dimm_populated[dimm_num] != SDRAM_NONE)
  1490. t_wr_ns = max(t_wr_ns,
  1491. spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
  1492. }
  1493. /*
  1494. * convert from nanoseconds to ddr clocks
  1495. * round up if necessary
  1496. */
  1497. t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
  1498. ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
  1499. if (sdram_freq != ddr_check)
  1500. t_wr_clk++;
  1501. switch (t_wr_clk) {
  1502. case 0:
  1503. case 1:
  1504. case 2:
  1505. case 3:
  1506. mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
  1507. break;
  1508. case 4:
  1509. mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
  1510. break;
  1511. case 5:
  1512. mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
  1513. break;
  1514. default:
  1515. mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
  1516. break;
  1517. }
  1518. *write_recovery = t_wr_clk;
  1519. }
  1520. debug("CAS latency = %d\n", *selected_cas);
  1521. debug("Write recovery = %d\n", *write_recovery);
  1522. mtsdram(SDRAM_MMODE, mmode);
  1523. }
  1524. /*-----------------------------------------------------------------------------+
  1525. * program_rtr.
  1526. *-----------------------------------------------------------------------------*/
  1527. static void program_rtr(unsigned long *dimm_populated,
  1528. unsigned char *iic0_dimm_addr,
  1529. unsigned long num_dimm_banks)
  1530. {
  1531. PPC4xx_SYS_INFO board_cfg;
  1532. unsigned long max_refresh_rate;
  1533. unsigned long dimm_num;
  1534. unsigned long refresh_rate_type;
  1535. unsigned long refresh_rate;
  1536. unsigned long rint;
  1537. unsigned long sdram_freq;
  1538. unsigned long sdr_ddrpll;
  1539. unsigned long val;
  1540. /*------------------------------------------------------------------
  1541. * Get the board configuration info.
  1542. *-----------------------------------------------------------------*/
  1543. get_sys_info(&board_cfg);
  1544. /*------------------------------------------------------------------
  1545. * Set the SDRAM Refresh Timing Register, SDRAM_RTR
  1546. *-----------------------------------------------------------------*/
  1547. mfsdr(SDR0_DDR0, sdr_ddrpll);
  1548. sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
  1549. max_refresh_rate = 0;
  1550. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1551. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1552. refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
  1553. refresh_rate_type &= 0x7F;
  1554. switch (refresh_rate_type) {
  1555. case 0:
  1556. refresh_rate = 15625;
  1557. break;
  1558. case 1:
  1559. refresh_rate = 3906;
  1560. break;
  1561. case 2:
  1562. refresh_rate = 7812;
  1563. break;
  1564. case 3:
  1565. refresh_rate = 31250;
  1566. break;
  1567. case 4:
  1568. refresh_rate = 62500;
  1569. break;
  1570. case 5:
  1571. refresh_rate = 125000;
  1572. break;
  1573. default:
  1574. refresh_rate = 0;
  1575. printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
  1576. (unsigned int)dimm_num);
  1577. printf("Replace the DIMM module with a supported DIMM.\n\n");
  1578. spd_ddr_init_hang ();
  1579. break;
  1580. }
  1581. max_refresh_rate = max(max_refresh_rate, refresh_rate);
  1582. }
  1583. }
  1584. rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
  1585. mfsdram(SDRAM_RTR, val);
  1586. mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
  1587. (SDRAM_RTR_RINT_ENCODE(rint)));
  1588. }
  1589. /*------------------------------------------------------------------
  1590. * This routine programs the SDRAM_TRx registers.
  1591. *-----------------------------------------------------------------*/
  1592. static void program_tr(unsigned long *dimm_populated,
  1593. unsigned char *iic0_dimm_addr,
  1594. unsigned long num_dimm_banks)
  1595. {
  1596. unsigned long dimm_num;
  1597. unsigned long sdram_ddr1;
  1598. unsigned long t_rp_ns;
  1599. unsigned long t_rcd_ns;
  1600. unsigned long t_rrd_ns;
  1601. unsigned long t_ras_ns;
  1602. unsigned long t_rc_ns;
  1603. unsigned long t_rfc_ns;
  1604. unsigned long t_wpc_ns;
  1605. unsigned long t_wtr_ns;
  1606. unsigned long t_rpc_ns;
  1607. unsigned long t_rp_clk;
  1608. unsigned long t_rcd_clk;
  1609. unsigned long t_rrd_clk;
  1610. unsigned long t_ras_clk;
  1611. unsigned long t_rc_clk;
  1612. unsigned long t_rfc_clk;
  1613. unsigned long t_wpc_clk;
  1614. unsigned long t_wtr_clk;
  1615. unsigned long t_rpc_clk;
  1616. unsigned long sdtr1, sdtr2, sdtr3;
  1617. unsigned long ddr_check;
  1618. unsigned long sdram_freq;
  1619. unsigned long sdr_ddrpll;
  1620. PPC4xx_SYS_INFO board_cfg;
  1621. /*------------------------------------------------------------------
  1622. * Get the board configuration info.
  1623. *-----------------------------------------------------------------*/
  1624. get_sys_info(&board_cfg);
  1625. mfsdr(SDR0_DDR0, sdr_ddrpll);
  1626. sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
  1627. /*------------------------------------------------------------------
  1628. * Handle the timing. We need to find the worst case timing of all
  1629. * the dimm modules installed.
  1630. *-----------------------------------------------------------------*/
  1631. t_rp_ns = 0;
  1632. t_rrd_ns = 0;
  1633. t_rcd_ns = 0;
  1634. t_ras_ns = 0;
  1635. t_rc_ns = 0;
  1636. t_rfc_ns = 0;
  1637. t_wpc_ns = 0;
  1638. t_wtr_ns = 0;
  1639. t_rpc_ns = 0;
  1640. sdram_ddr1 = TRUE;
  1641. /* loop through all the DIMM slots on the board */
  1642. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1643. /* If a dimm is installed in a particular slot ... */
  1644. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1645. if (dimm_populated[dimm_num] == SDRAM_DDR2)
  1646. sdram_ddr1 = TRUE;
  1647. else
  1648. sdram_ddr1 = FALSE;
  1649. t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
  1650. t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
  1651. t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
  1652. t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
  1653. t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
  1654. t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
  1655. }
  1656. }
  1657. /*------------------------------------------------------------------
  1658. * Set the SDRAM Timing Reg 1, SDRAM_TR1
  1659. *-----------------------------------------------------------------*/
  1660. mfsdram(SDRAM_SDTR1, sdtr1);
  1661. sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
  1662. SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
  1663. /* default values */
  1664. sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
  1665. sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
  1666. /* normal operations */
  1667. sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
  1668. sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
  1669. mtsdram(SDRAM_SDTR1, sdtr1);
  1670. /*------------------------------------------------------------------
  1671. * Set the SDRAM Timing Reg 2, SDRAM_TR2
  1672. *-----------------------------------------------------------------*/
  1673. mfsdram(SDRAM_SDTR2, sdtr2);
  1674. sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
  1675. SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
  1676. SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
  1677. SDRAM_SDTR2_RRD_MASK);
  1678. /*
  1679. * convert t_rcd from nanoseconds to ddr clocks
  1680. * round up if necessary
  1681. */
  1682. t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
  1683. ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
  1684. if (sdram_freq != ddr_check)
  1685. t_rcd_clk++;
  1686. switch (t_rcd_clk) {
  1687. case 0:
  1688. case 1:
  1689. sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
  1690. break;
  1691. case 2:
  1692. sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
  1693. break;
  1694. case 3:
  1695. sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
  1696. break;
  1697. case 4:
  1698. sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
  1699. break;
  1700. default:
  1701. sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
  1702. break;
  1703. }
  1704. if (sdram_ddr1 == TRUE) { /* DDR1 */
  1705. if (sdram_freq < 200000000) {
  1706. sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
  1707. sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
  1708. sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
  1709. } else {
  1710. sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
  1711. sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
  1712. sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
  1713. }
  1714. } else { /* DDR2 */
  1715. /* loop through all the DIMM slots on the board */
  1716. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1717. /* If a dimm is installed in a particular slot ... */
  1718. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1719. t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
  1720. t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
  1721. t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
  1722. }
  1723. }
  1724. /*
  1725. * convert from nanoseconds to ddr clocks
  1726. * round up if necessary
  1727. */
  1728. t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
  1729. ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
  1730. if (sdram_freq != ddr_check)
  1731. t_wpc_clk++;
  1732. switch (t_wpc_clk) {
  1733. case 0:
  1734. case 1:
  1735. case 2:
  1736. sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
  1737. break;
  1738. case 3:
  1739. sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
  1740. break;
  1741. case 4:
  1742. sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
  1743. break;
  1744. case 5:
  1745. sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
  1746. break;
  1747. default:
  1748. sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
  1749. break;
  1750. }
  1751. /*
  1752. * convert from nanoseconds to ddr clocks
  1753. * round up if necessary
  1754. */
  1755. t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
  1756. ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
  1757. if (sdram_freq != ddr_check)
  1758. t_wtr_clk++;
  1759. switch (t_wtr_clk) {
  1760. case 0:
  1761. case 1:
  1762. sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
  1763. break;
  1764. case 2:
  1765. sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
  1766. break;
  1767. case 3:
  1768. sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
  1769. break;
  1770. default:
  1771. sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
  1772. break;
  1773. }
  1774. /*
  1775. * convert from nanoseconds to ddr clocks
  1776. * round up if necessary
  1777. */
  1778. t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
  1779. ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
  1780. if (sdram_freq != ddr_check)
  1781. t_rpc_clk++;
  1782. switch (t_rpc_clk) {
  1783. case 0:
  1784. case 1:
  1785. case 2:
  1786. sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
  1787. break;
  1788. case 3:
  1789. sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
  1790. break;
  1791. default:
  1792. sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
  1793. break;
  1794. }
  1795. }
  1796. /* default value */
  1797. sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
  1798. /*
  1799. * convert t_rrd from nanoseconds to ddr clocks
  1800. * round up if necessary
  1801. */
  1802. t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
  1803. ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
  1804. if (sdram_freq != ddr_check)
  1805. t_rrd_clk++;
  1806. if (t_rrd_clk == 3)
  1807. sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
  1808. else
  1809. sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
  1810. /*
  1811. * convert t_rp from nanoseconds to ddr clocks
  1812. * round up if necessary
  1813. */
  1814. t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
  1815. ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
  1816. if (sdram_freq != ddr_check)
  1817. t_rp_clk++;
  1818. switch (t_rp_clk) {
  1819. case 0:
  1820. case 1:
  1821. case 2:
  1822. case 3:
  1823. sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
  1824. break;
  1825. case 4:
  1826. sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
  1827. break;
  1828. case 5:
  1829. sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
  1830. break;
  1831. case 6:
  1832. sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
  1833. break;
  1834. default:
  1835. sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
  1836. break;
  1837. }
  1838. mtsdram(SDRAM_SDTR2, sdtr2);
  1839. /*------------------------------------------------------------------
  1840. * Set the SDRAM Timing Reg 3, SDRAM_TR3
  1841. *-----------------------------------------------------------------*/
  1842. mfsdram(SDRAM_SDTR3, sdtr3);
  1843. sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
  1844. SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
  1845. /*
  1846. * convert t_ras from nanoseconds to ddr clocks
  1847. * round up if necessary
  1848. */
  1849. t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
  1850. ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
  1851. if (sdram_freq != ddr_check)
  1852. t_ras_clk++;
  1853. sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
  1854. /*
  1855. * convert t_rc from nanoseconds to ddr clocks
  1856. * round up if necessary
  1857. */
  1858. t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
  1859. ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
  1860. if (sdram_freq != ddr_check)
  1861. t_rc_clk++;
  1862. sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
  1863. /* default xcs value */
  1864. sdtr3 |= SDRAM_SDTR3_XCS;
  1865. /*
  1866. * convert t_rfc from nanoseconds to ddr clocks
  1867. * round up if necessary
  1868. */
  1869. t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
  1870. ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
  1871. if (sdram_freq != ddr_check)
  1872. t_rfc_clk++;
  1873. sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
  1874. mtsdram(SDRAM_SDTR3, sdtr3);
  1875. }
  1876. /*-----------------------------------------------------------------------------+
  1877. * program_bxcf.
  1878. *-----------------------------------------------------------------------------*/
  1879. static void program_bxcf(unsigned long *dimm_populated,
  1880. unsigned char *iic0_dimm_addr,
  1881. unsigned long num_dimm_banks)
  1882. {
  1883. unsigned long dimm_num;
  1884. unsigned long num_col_addr;
  1885. unsigned long num_ranks;
  1886. unsigned long num_banks;
  1887. unsigned long mode;
  1888. unsigned long ind_rank;
  1889. unsigned long ind;
  1890. unsigned long ind_bank;
  1891. unsigned long bank_0_populated;
  1892. /*------------------------------------------------------------------
  1893. * Set the BxCF regs. First, wipe out the bank config registers.
  1894. *-----------------------------------------------------------------*/
  1895. mtsdram(SDRAM_MB0CF, 0x00000000);
  1896. mtsdram(SDRAM_MB1CF, 0x00000000);
  1897. mtsdram(SDRAM_MB2CF, 0x00000000);
  1898. mtsdram(SDRAM_MB3CF, 0x00000000);
  1899. mode = SDRAM_BXCF_M_BE_ENABLE;
  1900. bank_0_populated = 0;
  1901. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1902. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1903. num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
  1904. num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
  1905. if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
  1906. num_ranks = (num_ranks & 0x0F) +1;
  1907. else
  1908. num_ranks = num_ranks & 0x0F;
  1909. num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
  1910. for (ind_bank = 0; ind_bank < 2; ind_bank++) {
  1911. if (num_banks == 4)
  1912. ind = 0;
  1913. else
  1914. ind = 5 << 8;
  1915. switch (num_col_addr) {
  1916. case 0x08:
  1917. mode |= (SDRAM_BXCF_M_AM_0 + ind);
  1918. break;
  1919. case 0x09:
  1920. mode |= (SDRAM_BXCF_M_AM_1 + ind);
  1921. break;
  1922. case 0x0A:
  1923. mode |= (SDRAM_BXCF_M_AM_2 + ind);
  1924. break;
  1925. case 0x0B:
  1926. mode |= (SDRAM_BXCF_M_AM_3 + ind);
  1927. break;
  1928. case 0x0C:
  1929. mode |= (SDRAM_BXCF_M_AM_4 + ind);
  1930. break;
  1931. default:
  1932. printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
  1933. (unsigned int)dimm_num);
  1934. printf("ERROR: Unsupported value for number of "
  1935. "column addresses: %d.\n", (unsigned int)num_col_addr);
  1936. printf("Replace the DIMM module with a supported DIMM.\n\n");
  1937. spd_ddr_init_hang ();
  1938. }
  1939. }
  1940. if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
  1941. bank_0_populated = 1;
  1942. for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
  1943. mtsdram(SDRAM_MB0CF +
  1944. ((dimm_num + bank_0_populated + ind_rank) << 2),
  1945. mode);
  1946. }
  1947. }
  1948. }
  1949. }
  1950. /*------------------------------------------------------------------
  1951. * program memory queue.
  1952. *-----------------------------------------------------------------*/
  1953. static void program_memory_queue(unsigned long *dimm_populated,
  1954. unsigned char *iic0_dimm_addr,
  1955. unsigned long num_dimm_banks)
  1956. {
  1957. unsigned long dimm_num;
  1958. phys_size_t rank_base_addr;
  1959. unsigned long rank_reg;
  1960. phys_size_t rank_size_bytes;
  1961. unsigned long rank_size_id;
  1962. unsigned long num_ranks;
  1963. unsigned long baseadd_size;
  1964. unsigned long i;
  1965. unsigned long bank_0_populated = 0;
  1966. phys_size_t total_size = 0;
  1967. /*------------------------------------------------------------------
  1968. * Reset the rank_base_address.
  1969. *-----------------------------------------------------------------*/
  1970. rank_reg = SDRAM_R0BAS;
  1971. rank_base_addr = 0x00000000;
  1972. for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
  1973. if (dimm_populated[dimm_num] != SDRAM_NONE) {
  1974. num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
  1975. if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
  1976. num_ranks = (num_ranks & 0x0F) + 1;
  1977. else
  1978. num_ranks = num_ranks & 0x0F;
  1979. rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
  1980. /*------------------------------------------------------------------
  1981. * Set the sizes
  1982. *-----------------------------------------------------------------*/
  1983. baseadd_size = 0;
  1984. switch (rank_size_id) {
  1985. case 0x01:
  1986. baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
  1987. total_size = 1024;
  1988. break;
  1989. case 0x02:
  1990. baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
  1991. total_size = 2048;
  1992. break;
  1993. case 0x04:
  1994. baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
  1995. total_size = 4096;
  1996. break;
  1997. case 0x08:
  1998. baseadd_size |= SDRAM_RXBAS_SDSZ_32;
  1999. total_size = 32;
  2000. break;
  2001. case 0x10:
  2002. baseadd_size |= SDRAM_RXBAS_SDSZ_64;
  2003. total_size = 64;
  2004. break;
  2005. case 0x20:
  2006. baseadd_size |= SDRAM_RXBAS_SDSZ_128;
  2007. total_size = 128;
  2008. break;
  2009. case 0x40:
  2010. baseadd_size |= SDRAM_RXBAS_SDSZ_256;
  2011. total_size = 256;
  2012. break;
  2013. case 0x80:
  2014. baseadd_size |= SDRAM_RXBAS_SDSZ_512;
  2015. total_size = 512;
  2016. break;
  2017. default:
  2018. printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
  2019. (unsigned int)dimm_num);
  2020. printf("ERROR: Unsupported value for the banksize: %d.\n",
  2021. (unsigned int)rank_size_id);
  2022. printf("Replace the DIMM module with a supported DIMM.\n\n");
  2023. spd_ddr_init_hang ();
  2024. }
  2025. rank_size_bytes = total_size << 20;
  2026. if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
  2027. bank_0_populated = 1;
  2028. for (i = 0; i < num_ranks; i++) {
  2029. mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
  2030. (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
  2031. baseadd_size));
  2032. rank_base_addr += rank_size_bytes;
  2033. }
  2034. }
  2035. }
  2036. #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  2037. defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  2038. defined(CONFIG_460SX)
  2039. /*
  2040. * Enable high bandwidth access
  2041. * This is currently not used, but with this setup
  2042. * it is possible to use it later on in e.g. the Linux
  2043. * EMAC driver for performance gain.
  2044. */
  2045. mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
  2046. mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
  2047. /*
  2048. * Set optimal value for Memory Queue HB/LL Configuration registers
  2049. */
  2050. mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
  2051. SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
  2052. SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
  2053. mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
  2054. SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
  2055. SDRAM_CONF1LL_RPLM);
  2056. mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
  2057. #endif
  2058. }
  2059. /*-----------------------------------------------------------------------------+
  2060. * is_ecc_enabled.
  2061. *-----------------------------------------------------------------------------*/
  2062. static unsigned long is_ecc_enabled(void)
  2063. {
  2064. unsigned long dimm_num;
  2065. unsigned long ecc;
  2066. unsigned long val;
  2067. ecc = 0;
  2068. /* loop through all the DIMM slots on the board */
  2069. for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
  2070. mfsdram(SDRAM_MCOPT1, val);
  2071. ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
  2072. }
  2073. return ecc;
  2074. }
  2075. #ifdef CONFIG_DDR_ECC
  2076. /*-----------------------------------------------------------------------------+
  2077. * program_ecc.
  2078. *-----------------------------------------------------------------------------*/
  2079. static void program_ecc(unsigned long *dimm_populated,
  2080. unsigned char *iic0_dimm_addr,
  2081. unsigned long num_dimm_banks,
  2082. unsigned long tlb_word2_i_value)
  2083. {
  2084. unsigned long mcopt1;
  2085. unsigned long mcopt2;
  2086. unsigned long mcstat;
  2087. unsigned long dimm_num;
  2088. unsigned long ecc;
  2089. ecc = 0;
  2090. /* loop through all the DIMM slots on the board */
  2091. for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
  2092. /* If a dimm is installed in a particular slot ... */
  2093. if (dimm_populated[dimm_num] != SDRAM_NONE)
  2094. ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
  2095. }
  2096. if (ecc == 0)
  2097. return;
  2098. if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) {
  2099. printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
  2100. return;
  2101. }
  2102. mfsdram(SDRAM_MCOPT1, mcopt1);
  2103. mfsdram(SDRAM_MCOPT2, mcopt2);
  2104. if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
  2105. /* DDR controller must be enabled and not in self-refresh. */
  2106. mfsdram(SDRAM_MCSTAT, mcstat);
  2107. if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
  2108. && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
  2109. && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
  2110. == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
  2111. program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
  2112. }
  2113. }
  2114. return;
  2115. }
  2116. static void wait_ddr_idle(void)
  2117. {
  2118. u32 val;
  2119. do {
  2120. mfsdram(SDRAM_MCSTAT, val);
  2121. } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
  2122. }
  2123. /*-----------------------------------------------------------------------------+
  2124. * program_ecc_addr.
  2125. *-----------------------------------------------------------------------------*/
  2126. static void program_ecc_addr(unsigned long start_address,
  2127. unsigned long num_bytes,
  2128. unsigned long tlb_word2_i_value)
  2129. {
  2130. unsigned long current_address;
  2131. unsigned long end_address;
  2132. unsigned long address_increment;
  2133. unsigned long mcopt1;
  2134. char str[] = "ECC generation -";
  2135. char slash[] = "\\|/-\\|/-";
  2136. int loop = 0;
  2137. int loopi = 0;
  2138. current_address = start_address;
  2139. mfsdram(SDRAM_MCOPT1, mcopt1);
  2140. if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
  2141. mtsdram(SDRAM_MCOPT1,
  2142. (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
  2143. sync();
  2144. eieio();
  2145. wait_ddr_idle();
  2146. puts(str);
  2147. if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
  2148. /* ECC bit set method for non-cached memory */
  2149. if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
  2150. address_increment = 4;
  2151. else
  2152. address_increment = 8;
  2153. end_address = current_address + num_bytes;
  2154. while (current_address < end_address) {
  2155. *((unsigned long *)current_address) = 0x00000000;
  2156. current_address += address_increment;
  2157. if ((loop++ % (2 << 20)) == 0) {
  2158. putc('\b');
  2159. putc(slash[loopi++ % 8]);
  2160. }
  2161. }
  2162. } else {
  2163. /* ECC bit set method for cached memory */
  2164. dcbz_area(start_address, num_bytes);
  2165. /* Write modified dcache lines back to memory */
  2166. clean_dcache_range(start_address, start_address + num_bytes);
  2167. }
  2168. blank_string(strlen(str));
  2169. sync();
  2170. eieio();
  2171. wait_ddr_idle();
  2172. /* clear ECC error repoting registers */
  2173. mtsdram(SDRAM_ECCCR, 0xffffffff);
  2174. mtdcr(0x4c, 0xffffffff);
  2175. mtsdram(SDRAM_MCOPT1,
  2176. (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
  2177. sync();
  2178. eieio();
  2179. wait_ddr_idle();
  2180. }
  2181. }
  2182. #endif
  2183. #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  2184. /*-----------------------------------------------------------------------------+
  2185. * program_DQS_calibration.
  2186. *-----------------------------------------------------------------------------*/
  2187. static void program_DQS_calibration(unsigned long *dimm_populated,
  2188. unsigned char *iic0_dimm_addr,
  2189. unsigned long num_dimm_banks)
  2190. {
  2191. unsigned long val;
  2192. #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
  2193. mtsdram(SDRAM_RQDC, 0x80000037);
  2194. mtsdram(SDRAM_RDCC, 0x40000000);
  2195. mtsdram(SDRAM_RFDC, 0x000001DF);
  2196. test();
  2197. #else
  2198. /*------------------------------------------------------------------
  2199. * Program RDCC register
  2200. * Read sample cycle auto-update enable
  2201. *-----------------------------------------------------------------*/
  2202. mfsdram(SDRAM_RDCC, val);
  2203. mtsdram(SDRAM_RDCC,
  2204. (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
  2205. | SDRAM_RDCC_RSAE_ENABLE);
  2206. /*------------------------------------------------------------------
  2207. * Program RQDC register
  2208. * Internal DQS delay mechanism enable
  2209. *-----------------------------------------------------------------*/
  2210. mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
  2211. /*------------------------------------------------------------------
  2212. * Program RFDC register
  2213. * Set Feedback Fractional Oversample
  2214. * Auto-detect read sample cycle enable
  2215. * Set RFOS to 1/4 of memclk cycle (0x3f)
  2216. *-----------------------------------------------------------------*/
  2217. mfsdram(SDRAM_RFDC, val);
  2218. mtsdram(SDRAM_RFDC,
  2219. (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
  2220. SDRAM_RFDC_RFFD_MASK))
  2221. | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
  2222. SDRAM_RFDC_RFFD_ENCODE(0)));
  2223. DQS_calibration_process();
  2224. #endif
  2225. }
  2226. static int short_mem_test(void)
  2227. {
  2228. u32 *membase;
  2229. u32 bxcr_num;
  2230. u32 bxcf;
  2231. int i;
  2232. int j;
  2233. phys_size_t base_addr;
  2234. u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
  2235. {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  2236. 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
  2237. {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  2238. 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
  2239. {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  2240. 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
  2241. {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  2242. 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
  2243. {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  2244. 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
  2245. {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  2246. 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
  2247. {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  2248. 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
  2249. {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  2250. 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
  2251. int l;
  2252. for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
  2253. mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
  2254. /* Banks enabled */
  2255. if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
  2256. /* Bank is enabled */
  2257. /*
  2258. * Only run test on accessable memory (below 2GB)
  2259. */
  2260. base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
  2261. if (base_addr >= CONFIG_MAX_MEM_MAPPED)
  2262. continue;
  2263. /*------------------------------------------------------------------
  2264. * Run the short memory test.
  2265. *-----------------------------------------------------------------*/
  2266. membase = (u32 *)(u32)base_addr;
  2267. for (i = 0; i < NUMMEMTESTS; i++) {
  2268. for (j = 0; j < NUMMEMWORDS; j++) {
  2269. membase[j] = test[i][j];
  2270. ppcDcbf((u32)&(membase[j]));
  2271. }
  2272. sync();
  2273. for (l=0; l<NUMLOOPS; l++) {
  2274. for (j = 0; j < NUMMEMWORDS; j++) {
  2275. if (membase[j] != test[i][j]) {
  2276. ppcDcbf((u32)&(membase[j]));
  2277. return 0;
  2278. }
  2279. ppcDcbf((u32)&(membase[j]));
  2280. }
  2281. sync();
  2282. }
  2283. }
  2284. } /* if bank enabled */
  2285. } /* for bxcf_num */
  2286. return 1;
  2287. }
  2288. #ifndef HARD_CODED_DQS
  2289. /*-----------------------------------------------------------------------------+
  2290. * DQS_calibration_process.
  2291. *-----------------------------------------------------------------------------*/
  2292. static void DQS_calibration_process(void)
  2293. {
  2294. unsigned long rfdc_reg;
  2295. unsigned long rffd;
  2296. unsigned long val;
  2297. long rffd_average;
  2298. long max_start;
  2299. long min_end;
  2300. unsigned long begin_rqfd[MAXRANKS];
  2301. unsigned long begin_rffd[MAXRANKS];
  2302. unsigned long end_rqfd[MAXRANKS];
  2303. unsigned long end_rffd[MAXRANKS];
  2304. char window_found;
  2305. unsigned long dlycal;
  2306. unsigned long dly_val;
  2307. unsigned long max_pass_length;
  2308. unsigned long current_pass_length;
  2309. unsigned long current_fail_length;
  2310. unsigned long current_start;
  2311. long max_end;
  2312. unsigned char fail_found;
  2313. unsigned char pass_found;
  2314. #if !defined(CONFIG_DDR_RQDC_FIXED)
  2315. u32 rqdc_reg;
  2316. u32 rqfd;
  2317. u32 rqfd_start;
  2318. u32 rqfd_average;
  2319. int loopi = 0;
  2320. char str[] = "Auto calibration -";
  2321. char slash[] = "\\|/-\\|/-";
  2322. /*------------------------------------------------------------------
  2323. * Test to determine the best read clock delay tuning bits.
  2324. *
  2325. * Before the DDR controller can be used, the read clock delay needs to be
  2326. * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
  2327. * This value cannot be hardcoded into the program because it changes
  2328. * depending on the board's setup and environment.
  2329. * To do this, all delay values are tested to see if they
  2330. * work or not. By doing this, you get groups of fails with groups of
  2331. * passing values. The idea is to find the start and end of a passing
  2332. * window and take the center of it to use as the read clock delay.
  2333. *
  2334. * A failure has to be seen first so that when we hit a pass, we know
  2335. * that it is truely the start of the window. If we get passing values
  2336. * to start off with, we don't know if we are at the start of the window.
  2337. *
  2338. * The code assumes that a failure will always be found.
  2339. * If a failure is not found, there is no easy way to get the middle
  2340. * of the passing window. I guess we can pretty much pick any value
  2341. * but some values will be better than others. Since the lowest speed
  2342. * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
  2343. * from experimentation it is safe to say you will always have a failure.
  2344. *-----------------------------------------------------------------*/
  2345. /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
  2346. rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
  2347. puts(str);
  2348. calibration_loop:
  2349. mfsdram(SDRAM_RQDC, rqdc_reg);
  2350. mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
  2351. SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
  2352. #else /* CONFIG_DDR_RQDC_FIXED */
  2353. /*
  2354. * On Katmai the complete auto-calibration somehow doesn't seem to
  2355. * produce the best results, meaning optimal values for RQFD/RFFD.
  2356. * This was discovered by GDA using a high bandwidth scope,
  2357. * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
  2358. * so now on Katmai "only" RFFD is auto-calibrated.
  2359. */
  2360. mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
  2361. #endif /* CONFIG_DDR_RQDC_FIXED */
  2362. max_start = 0;
  2363. min_end = 0;
  2364. begin_rqfd[0] = 0;
  2365. begin_rffd[0] = 0;
  2366. begin_rqfd[1] = 0;
  2367. begin_rffd[1] = 0;
  2368. end_rqfd[0] = 0;
  2369. end_rffd[0] = 0;
  2370. end_rqfd[1] = 0;
  2371. end_rffd[1] = 0;
  2372. window_found = FALSE;
  2373. max_pass_length = 0;
  2374. max_start = 0;
  2375. max_end = 0;
  2376. current_pass_length = 0;
  2377. current_fail_length = 0;
  2378. current_start = 0;
  2379. window_found = FALSE;
  2380. fail_found = FALSE;
  2381. pass_found = FALSE;
  2382. /*
  2383. * get the delay line calibration register value
  2384. */
  2385. mfsdram(SDRAM_DLCR, dlycal);
  2386. dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
  2387. for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
  2388. mfsdram(SDRAM_RFDC, rfdc_reg);
  2389. rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
  2390. /*------------------------------------------------------------------
  2391. * Set the timing reg for the test.
  2392. *-----------------------------------------------------------------*/
  2393. mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
  2394. /*------------------------------------------------------------------
  2395. * See if the rffd value passed.
  2396. *-----------------------------------------------------------------*/
  2397. if (short_mem_test()) {
  2398. if (fail_found == TRUE) {
  2399. pass_found = TRUE;
  2400. if (current_pass_length == 0)
  2401. current_start = rffd;
  2402. current_fail_length = 0;
  2403. current_pass_length++;
  2404. if (current_pass_length > max_pass_length) {
  2405. max_pass_length = current_pass_length;
  2406. max_start = current_start;
  2407. max_end = rffd;
  2408. }
  2409. }
  2410. } else {
  2411. current_pass_length = 0;
  2412. current_fail_length++;
  2413. if (current_fail_length >= (dly_val >> 2)) {
  2414. if (fail_found == FALSE) {
  2415. fail_found = TRUE;
  2416. } else if (pass_found == TRUE) {
  2417. window_found = TRUE;
  2418. break;
  2419. }
  2420. }
  2421. }
  2422. } /* for rffd */
  2423. /*------------------------------------------------------------------
  2424. * Set the average RFFD value
  2425. *-----------------------------------------------------------------*/
  2426. rffd_average = ((max_start + max_end) >> 1);
  2427. if (rffd_average < 0)
  2428. rffd_average = 0;
  2429. if (rffd_average > SDRAM_RFDC_RFFD_MAX)
  2430. rffd_average = SDRAM_RFDC_RFFD_MAX;
  2431. /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
  2432. mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
  2433. #if !defined(CONFIG_DDR_RQDC_FIXED)
  2434. max_pass_length = 0;
  2435. max_start = 0;
  2436. max_end = 0;
  2437. current_pass_length = 0;
  2438. current_fail_length = 0;
  2439. current_start = 0;
  2440. window_found = FALSE;
  2441. fail_found = FALSE;
  2442. pass_found = FALSE;
  2443. for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
  2444. mfsdram(SDRAM_RQDC, rqdc_reg);
  2445. rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
  2446. /*------------------------------------------------------------------
  2447. * Set the timing reg for the test.
  2448. *-----------------------------------------------------------------*/
  2449. mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
  2450. /*------------------------------------------------------------------
  2451. * See if the rffd value passed.
  2452. *-----------------------------------------------------------------*/
  2453. if (short_mem_test()) {
  2454. if (fail_found == TRUE) {
  2455. pass_found = TRUE;
  2456. if (current_pass_length == 0)
  2457. current_start = rqfd;
  2458. current_fail_length = 0;
  2459. current_pass_length++;
  2460. if (current_pass_length > max_pass_length) {
  2461. max_pass_length = current_pass_length;
  2462. max_start = current_start;
  2463. max_end = rqfd;
  2464. }
  2465. }
  2466. } else {
  2467. current_pass_length = 0;
  2468. current_fail_length++;
  2469. if (fail_found == FALSE) {
  2470. fail_found = TRUE;
  2471. } else if (pass_found == TRUE) {
  2472. window_found = TRUE;
  2473. break;
  2474. }
  2475. }
  2476. }
  2477. rqfd_average = ((max_start + max_end) >> 1);
  2478. /*------------------------------------------------------------------
  2479. * Make sure we found the valid read passing window. Halt if not
  2480. *-----------------------------------------------------------------*/
  2481. if (window_found == FALSE) {
  2482. if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
  2483. putc('\b');
  2484. putc(slash[loopi++ % 8]);
  2485. /* try again from with a different RQFD start value */
  2486. rqfd_start++;
  2487. goto calibration_loop;
  2488. }
  2489. printf("\nERROR: Cannot determine a common read delay for the "
  2490. "DIMM(s) installed.\n");
  2491. debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
  2492. ppc4xx_ibm_ddr2_register_dump();
  2493. spd_ddr_init_hang ();
  2494. }
  2495. if (rqfd_average < 0)
  2496. rqfd_average = 0;
  2497. if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
  2498. rqfd_average = SDRAM_RQDC_RQFD_MAX;
  2499. mtsdram(SDRAM_RQDC,
  2500. (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
  2501. SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
  2502. blank_string(strlen(str));
  2503. #endif /* CONFIG_DDR_RQDC_FIXED */
  2504. /*
  2505. * Now complete RDSS configuration as mentioned on page 7 of the AMCC
  2506. * PowerPC440SP/SPe DDR2 application note:
  2507. * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  2508. */
  2509. mfsdram(SDRAM_RTSR, val);
  2510. if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
  2511. mfsdram(SDRAM_RDCC, val);
  2512. if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
  2513. val += 0x40000000;
  2514. mtsdram(SDRAM_RDCC, val);
  2515. }
  2516. }
  2517. mfsdram(SDRAM_DLCR, val);
  2518. debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
  2519. mfsdram(SDRAM_RQDC, val);
  2520. debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
  2521. mfsdram(SDRAM_RFDC, val);
  2522. debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
  2523. mfsdram(SDRAM_RDCC, val);
  2524. debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
  2525. }
  2526. #else /* calibration test with hardvalues */
  2527. /*-----------------------------------------------------------------------------+
  2528. * DQS_calibration_process.
  2529. *-----------------------------------------------------------------------------*/
  2530. static void test(void)
  2531. {
  2532. unsigned long dimm_num;
  2533. unsigned long ecc_temp;
  2534. unsigned long i, j;
  2535. unsigned long *membase;
  2536. unsigned long bxcf[MAXRANKS];
  2537. unsigned long val;
  2538. char window_found;
  2539. char begin_found[MAXDIMMS];
  2540. char end_found[MAXDIMMS];
  2541. char search_end[MAXDIMMS];
  2542. unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
  2543. {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
  2544. 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
  2545. {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
  2546. 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
  2547. {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
  2548. 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
  2549. {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
  2550. 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
  2551. {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
  2552. 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
  2553. {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
  2554. 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
  2555. {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
  2556. 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
  2557. {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
  2558. 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
  2559. /*------------------------------------------------------------------
  2560. * Test to determine the best read clock delay tuning bits.
  2561. *
  2562. * Before the DDR controller can be used, the read clock delay needs to be
  2563. * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
  2564. * This value cannot be hardcoded into the program because it changes
  2565. * depending on the board's setup and environment.
  2566. * To do this, all delay values are tested to see if they
  2567. * work or not. By doing this, you get groups of fails with groups of
  2568. * passing values. The idea is to find the start and end of a passing
  2569. * window and take the center of it to use as the read clock delay.
  2570. *
  2571. * A failure has to be seen first so that when we hit a pass, we know
  2572. * that it is truely the start of the window. If we get passing values
  2573. * to start off with, we don't know if we are at the start of the window.
  2574. *
  2575. * The code assumes that a failure will always be found.
  2576. * If a failure is not found, there is no easy way to get the middle
  2577. * of the passing window. I guess we can pretty much pick any value
  2578. * but some values will be better than others. Since the lowest speed
  2579. * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
  2580. * from experimentation it is safe to say you will always have a failure.
  2581. *-----------------------------------------------------------------*/
  2582. mfsdram(SDRAM_MCOPT1, ecc_temp);
  2583. ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
  2584. mfsdram(SDRAM_MCOPT1, val);
  2585. mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
  2586. SDRAM_MCOPT1_MCHK_NON);
  2587. window_found = FALSE;
  2588. begin_found[0] = FALSE;
  2589. end_found[0] = FALSE;
  2590. search_end[0] = FALSE;
  2591. begin_found[1] = FALSE;
  2592. end_found[1] = FALSE;
  2593. search_end[1] = FALSE;
  2594. for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
  2595. mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
  2596. /* Banks enabled */
  2597. if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
  2598. /* Bank is enabled */
  2599. membase =
  2600. (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
  2601. /*------------------------------------------------------------------
  2602. * Run the short memory test.
  2603. *-----------------------------------------------------------------*/
  2604. for (i = 0; i < NUMMEMTESTS; i++) {
  2605. for (j = 0; j < NUMMEMWORDS; j++) {
  2606. membase[j] = test[i][j];
  2607. ppcDcbf((u32)&(membase[j]));
  2608. }
  2609. sync();
  2610. for (j = 0; j < NUMMEMWORDS; j++) {
  2611. if (membase[j] != test[i][j]) {
  2612. ppcDcbf((u32)&(membase[j]));
  2613. break;
  2614. }
  2615. ppcDcbf((u32)&(membase[j]));
  2616. }
  2617. sync();
  2618. if (j < NUMMEMWORDS)
  2619. break;
  2620. }
  2621. /*------------------------------------------------------------------
  2622. * See if the rffd value passed.
  2623. *-----------------------------------------------------------------*/
  2624. if (i < NUMMEMTESTS) {
  2625. if ((end_found[dimm_num] == FALSE) &&
  2626. (search_end[dimm_num] == TRUE)) {
  2627. end_found[dimm_num] = TRUE;
  2628. }
  2629. if ((end_found[0] == TRUE) &&
  2630. (end_found[1] == TRUE))
  2631. break;
  2632. } else {
  2633. if (begin_found[dimm_num] == FALSE) {
  2634. begin_found[dimm_num] = TRUE;
  2635. search_end[dimm_num] = TRUE;
  2636. }
  2637. }
  2638. } else {
  2639. begin_found[dimm_num] = TRUE;
  2640. end_found[dimm_num] = TRUE;
  2641. }
  2642. }
  2643. if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
  2644. window_found = TRUE;
  2645. /*------------------------------------------------------------------
  2646. * Make sure we found the valid read passing window. Halt if not
  2647. *-----------------------------------------------------------------*/
  2648. if (window_found == FALSE) {
  2649. printf("ERROR: Cannot determine a common read delay for the "
  2650. "DIMM(s) installed.\n");
  2651. spd_ddr_init_hang ();
  2652. }
  2653. /*------------------------------------------------------------------
  2654. * Restore the ECC variable to what it originally was
  2655. *-----------------------------------------------------------------*/
  2656. mtsdram(SDRAM_MCOPT1,
  2657. (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
  2658. | ecc_temp);
  2659. }
  2660. #endif /* !HARD_CODED_DQS */
  2661. #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
  2662. #else /* CONFIG_SPD_EEPROM */
  2663. /*-----------------------------------------------------------------------------
  2664. * Function: initdram
  2665. * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
  2666. * banks. The configuration is performed using static, compile-
  2667. * time parameters.
  2668. *---------------------------------------------------------------------------*/
  2669. phys_size_t initdram(int board_type)
  2670. {
  2671. /*
  2672. * Only run this SDRAM init code once. For NAND booting
  2673. * targets like Kilauea, we call initdram() early from the
  2674. * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
  2675. * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
  2676. * which calls initdram() again. This time the controller
  2677. * mustn't be reconfigured again since we're already running
  2678. * from SDRAM.
  2679. */
  2680. #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  2681. unsigned long val;
  2682. /* Set Memory Bank Configuration Registers */
  2683. mtsdram(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
  2684. mtsdram(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
  2685. mtsdram(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
  2686. mtsdram(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
  2687. /* Set Memory Clock Timing Register */
  2688. mtsdram(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
  2689. /* Set Refresh Time Register */
  2690. mtsdram(SDRAM_RTR, CFG_SDRAM0_RTR);
  2691. /* Set SDRAM Timing Registers */
  2692. mtsdram(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
  2693. mtsdram(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
  2694. mtsdram(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
  2695. /* Set Mode and Extended Mode Registers */
  2696. mtsdram(SDRAM_MMODE, CFG_SDRAM0_MMODE);
  2697. mtsdram(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
  2698. /* Set Memory Controller Options 1 Register */
  2699. mtsdram(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
  2700. /* Set Manual Initialization Control Registers */
  2701. mtsdram(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
  2702. mtsdram(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
  2703. mtsdram(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
  2704. mtsdram(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
  2705. mtsdram(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
  2706. mtsdram(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
  2707. mtsdram(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
  2708. mtsdram(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
  2709. mtsdram(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
  2710. mtsdram(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
  2711. mtsdram(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
  2712. mtsdram(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
  2713. mtsdram(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
  2714. mtsdram(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
  2715. mtsdram(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
  2716. mtsdram(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
  2717. /* Set On-Die Termination Registers */
  2718. mtsdram(SDRAM_CODT, CFG_SDRAM0_CODT);
  2719. mtsdram(SDRAM_MODT0, CFG_SDRAM0_MODT0);
  2720. mtsdram(SDRAM_MODT1, CFG_SDRAM0_MODT1);
  2721. /* Set Write Timing Register */
  2722. mtsdram(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
  2723. /*
  2724. * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
  2725. * SDRAM0_MCOPT2[IPTR] = 1
  2726. */
  2727. mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
  2728. SDRAM_MCOPT2_IPTR_EXECUTE));
  2729. /*
  2730. * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
  2731. * completion of initialization.
  2732. */
  2733. do {
  2734. mfsdram(SDRAM_MCSTAT, val);
  2735. } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
  2736. /* Set Delay Control Registers */
  2737. mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR);
  2738. #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  2739. mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC);
  2740. mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC);
  2741. mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC);
  2742. #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
  2743. /*
  2744. * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
  2745. */
  2746. mfsdram(SDRAM_MCOPT2, val);
  2747. mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
  2748. #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  2749. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  2750. /*------------------------------------------------------------------
  2751. | DQS calibration.
  2752. +-----------------------------------------------------------------*/
  2753. DQS_autocalibration();
  2754. #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
  2755. #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
  2756. #if defined(CONFIG_DDR_ECC)
  2757. ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
  2758. #endif /* defined(CONFIG_DDR_ECC) */
  2759. ppc4xx_ibm_ddr2_register_dump();
  2760. #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
  2761. /*
  2762. * Clear potential errors resulting from auto-calibration.
  2763. * If not done, then we could get an interrupt later on when
  2764. * exceptions are enabled.
  2765. */
  2766. set_mcsr(get_mcsr());
  2767. #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
  2768. #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
  2769. return (CFG_MBYTES_SDRAM << 20);
  2770. }
  2771. #endif /* CONFIG_SPD_EEPROM */
  2772. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  2773. #if defined(CONFIG_440)
  2774. u32 mfdcr_any(u32 dcr)
  2775. {
  2776. u32 val;
  2777. switch (dcr) {
  2778. case SDRAM_R0BAS + 0:
  2779. val = mfdcr(SDRAM_R0BAS + 0);
  2780. break;
  2781. case SDRAM_R0BAS + 1:
  2782. val = mfdcr(SDRAM_R0BAS + 1);
  2783. break;
  2784. case SDRAM_R0BAS + 2:
  2785. val = mfdcr(SDRAM_R0BAS + 2);
  2786. break;
  2787. case SDRAM_R0BAS + 3:
  2788. val = mfdcr(SDRAM_R0BAS + 3);
  2789. break;
  2790. default:
  2791. printf("DCR %d not defined in case statement!!!\n", dcr);
  2792. val = 0; /* just to satisfy the compiler */
  2793. }
  2794. return val;
  2795. }
  2796. void mtdcr_any(u32 dcr, u32 val)
  2797. {
  2798. switch (dcr) {
  2799. case SDRAM_R0BAS + 0:
  2800. mtdcr(SDRAM_R0BAS + 0, val);
  2801. break;
  2802. case SDRAM_R0BAS + 1:
  2803. mtdcr(SDRAM_R0BAS + 1, val);
  2804. break;
  2805. case SDRAM_R0BAS + 2:
  2806. mtdcr(SDRAM_R0BAS + 2, val);
  2807. break;
  2808. case SDRAM_R0BAS + 3:
  2809. mtdcr(SDRAM_R0BAS + 3, val);
  2810. break;
  2811. default:
  2812. printf("DCR %d not defined in case statement!!!\n", dcr);
  2813. }
  2814. }
  2815. #endif /* defined(CONFIG_440) */
  2816. void blank_string(int size)
  2817. {
  2818. int i;
  2819. for (i = 0; i < size; i++)
  2820. putc('\b');
  2821. for (i = 0; i < size; i++)
  2822. putc(' ');
  2823. for (i = 0; i < size; i++)
  2824. putc('\b');
  2825. }
  2826. #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
  2827. inline void ppc4xx_ibm_ddr2_register_dump(void)
  2828. {
  2829. #if defined(DEBUG)
  2830. printf("\nPPC4xx IBM DDR2 Register Dump:\n");
  2831. #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  2832. defined(CONFIG_460EX) || defined(CONFIG_460GT))
  2833. PPC4xx_IBM_DDR2_DUMP_REGISTER(R0BAS);
  2834. PPC4xx_IBM_DDR2_DUMP_REGISTER(R1BAS);
  2835. PPC4xx_IBM_DDR2_DUMP_REGISTER(R2BAS);
  2836. PPC4xx_IBM_DDR2_DUMP_REGISTER(R3BAS);
  2837. #endif /* (defined(CONFIG_440SP) || ... */
  2838. #if defined(CONFIG_405EX)
  2839. PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
  2840. PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
  2841. PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
  2842. PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
  2843. PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
  2844. PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
  2845. #endif /* defined(CONFIG_405EX) */
  2846. PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
  2847. PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
  2848. PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
  2849. PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
  2850. PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
  2851. PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
  2852. PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
  2853. PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
  2854. PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
  2855. PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
  2856. PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
  2857. PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
  2858. #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  2859. defined(CONFIG_460EX) || defined(CONFIG_460GT))
  2860. PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
  2861. PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
  2862. /*
  2863. * OPART is only used as a trigger register.
  2864. *
  2865. * No data is contained in this register, and reading or writing
  2866. * to is can cause bad things to happen (hangs). Just skip it and
  2867. * report "N/A".
  2868. */
  2869. printf("%20s = N/A\n", "SDRAM_OPART");
  2870. #endif /* defined(CONFIG_440SP) || ... */
  2871. PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
  2872. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
  2873. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
  2874. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
  2875. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
  2876. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
  2877. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
  2878. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
  2879. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
  2880. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
  2881. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
  2882. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
  2883. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
  2884. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
  2885. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
  2886. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
  2887. PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
  2888. PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
  2889. PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
  2890. PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
  2891. PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
  2892. PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
  2893. PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
  2894. PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
  2895. PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
  2896. PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
  2897. PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
  2898. PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
  2899. PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCCR);
  2900. #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
  2901. defined(CONFIG_460EX) || defined(CONFIG_460GT))
  2902. PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
  2903. #endif /* defined(CONFIG_440SP) || ... */
  2904. PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
  2905. PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
  2906. PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
  2907. #endif /* defined(DEBUG) */
  2908. }
  2909. #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */