MPC8260ADS.h 19 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Stuart Hughes <stuarth@lineo.com>
  4. * This file is based on similar values for other boards found in other
  5. * U-Boot config files, and some that I found in the mpc8260ads manual.
  6. *
  7. * Note: my board is a PILOT rev.
  8. * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
  9. *
  10. * (C) Copyright 2003-2004 Arabella Software Ltd.
  11. * Yuli Barcohen <yuli@arabellasw.com>
  12. * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
  13. * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
  14. * Ported to MPC8272ADS board.
  15. *
  16. * Copyright (c) 2005 MontaVista Software, Inc.
  17. * Vitaly Bordug <vbordug@ru.mvista.com>
  18. * Added support for PCI bridge on MPC8272ADS
  19. *
  20. * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
  21. *
  22. * See file CREDITS for list of people who contributed to this
  23. * project.
  24. *
  25. * This program is free software; you can redistribute it and/or
  26. * modify it under the terms of the GNU General Public License as
  27. * published by the Free Software Foundation; either version 2 of
  28. * the License, or (at your option) any later version.
  29. *
  30. * This program is distributed in the hope that it will be useful,
  31. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  33. * GNU General Public License for more details.
  34. *
  35. * You should have received a copy of the GNU General Public License
  36. * along with this program; if not, write to the Free Software
  37. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  38. * MA 02111-1307 USA
  39. */
  40. #ifndef __CONFIG_H
  41. #define __CONFIG_H
  42. /*
  43. * High Level Configuration Options
  44. * (easy to change)
  45. */
  46. #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
  47. #define CONFIG_CPM2 1 /* Has a CPM2 */
  48. /*
  49. * Figure out if we are booting low via flash HRCW or high via the BCSR.
  50. */
  51. #if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
  52. # define CONFIG_SYS_LOWBOOT 1
  53. #endif
  54. /* ADS flavours */
  55. #define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
  56. #define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
  57. #define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
  58. #define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
  59. #ifndef CONFIG_ADSTYPE
  60. #define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
  61. #endif /* CONFIG_ADSTYPE */
  62. #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  63. #define CONFIG_MPC8272 1
  64. #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
  65. /*
  66. * Actually MPC8275, but the code is littered with ifdefs that
  67. * apply to both, or which use this ifdef to assume board-specific
  68. * details. :-(
  69. */
  70. #define CONFIG_MPC8272 1
  71. #else
  72. #define CONFIG_MPC8260 1
  73. #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
  74. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  75. #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
  76. /* allow serial and ethaddr to be overwritten */
  77. #define CONFIG_ENV_OVERWRITE
  78. /*
  79. * select serial console configuration
  80. *
  81. * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  82. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  83. * for SCC).
  84. *
  85. * if CONFIG_CONS_NONE is defined, then the serial console routines must
  86. * defined elsewhere (for example, on the cogent platform, there are serial
  87. * ports on the motherboard which are used for the serial console - see
  88. * cogent/cma101/serial.[ch]).
  89. */
  90. #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
  91. #define CONFIG_CONS_ON_SCC /* define if console on SCC */
  92. #undef CONFIG_CONS_NONE /* define if console on something else */
  93. #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
  94. /*
  95. * select ethernet configuration
  96. *
  97. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  98. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  99. * for FCC)
  100. *
  101. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  102. * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  103. */
  104. #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
  105. #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
  106. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  107. #ifdef CONFIG_ETHER_ON_FCC
  108. #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
  109. #if CONFIG_ETHER_INDEX == 1
  110. # define CONFIG_SYS_PHY_ADDR 0
  111. # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
  112. # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  113. #elif CONFIG_ETHER_INDEX == 2
  114. #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
  115. # define CONFIG_SYS_PHY_ADDR 3
  116. # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
  117. #else /* RxCLK is CLK13, TxCLK is CLK14 */
  118. # define CONFIG_SYS_PHY_ADDR 0
  119. # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  120. #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
  121. # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  122. #endif /* CONFIG_ETHER_INDEX */
  123. #define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
  124. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
  125. #define CONFIG_MII /* MII PHY management */
  126. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  127. /*
  128. * GPIO pins used for bit-banged MII communications
  129. */
  130. #define MDIO_PORT 2 /* Port C */
  131. #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
  132. (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  133. #define MDC_DECLARE MDIO_DECLARE
  134. #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  135. #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
  136. #define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
  137. #else
  138. #define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
  139. #define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
  140. #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
  141. #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
  142. #define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
  143. #define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
  144. #define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
  145. else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
  146. #define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
  147. else iop->pdat &= ~CONFIG_SYS_MDC_PIN
  148. #define MIIDELAY udelay(1)
  149. #endif /* CONFIG_ETHER_ON_FCC */
  150. #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
  151. #undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
  152. #else
  153. #define CONFIG_HARD_I2C 1 /* To enable I2C support */
  154. #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
  155. #define CONFIG_SYS_I2C_SLAVE 0x7F
  156. #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
  157. #define CONFIG_SPD_ADDR 0x50
  158. #endif
  159. #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
  160. /*PCI*/
  161. #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
  162. #define CONFIG_PCI
  163. #define CONFIG_PCI_PNP
  164. #define CONFIG_PCI_BOOTDELAY 0
  165. #define CONFIG_PCI_SCAN_SHOW
  166. #endif
  167. #ifndef CONFIG_SDRAM_PBI
  168. #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
  169. #endif
  170. #ifndef CONFIG_8260_CLKIN
  171. #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
  172. #define CONFIG_8260_CLKIN 100000000 /* in Hz */
  173. #else
  174. #define CONFIG_8260_CLKIN 66000000 /* in Hz */
  175. #endif
  176. #endif
  177. #define CONFIG_BAUDRATE 115200
  178. #define CONFIG_OF_LIBFDT 1
  179. #define CONFIG_OF_BOARD_SETUP 1
  180. #if defined(CONFIG_OF_LIBFDT)
  181. #define OF_TBCLK (bd->bi_busfreq / 4)
  182. #endif
  183. /*
  184. * BOOTP options
  185. */
  186. #define CONFIG_BOOTP_BOOTFILESIZE
  187. #define CONFIG_BOOTP_BOOTPATH
  188. #define CONFIG_BOOTP_GATEWAY
  189. #define CONFIG_BOOTP_HOSTNAME
  190. /*
  191. * Command line configuration.
  192. */
  193. #include <config_cmd_default.h>
  194. #define CONFIG_CMD_ASKENV
  195. #define CONFIG_CMD_CACHE
  196. #define CONFIG_CMD_CDP
  197. #define CONFIG_CMD_DHCP
  198. #define CONFIG_CMD_DIAG
  199. #define CONFIG_CMD_I2C
  200. #define CONFIG_CMD_IMMAP
  201. #define CONFIG_CMD_IRQ
  202. #define CONFIG_CMD_JFFS2
  203. #define CONFIG_CMD_MII
  204. #define CONFIG_CMD_PCI
  205. #define CONFIG_CMD_PING
  206. #define CONFIG_CMD_PORTIO
  207. #define CONFIG_CMD_REGINFO
  208. #define CONFIG_CMD_SAVES
  209. #define CONFIG_CMD_SDRAM
  210. #undef CONFIG_CMD_XIMG
  211. #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  212. #undef CONFIG_CMD_SDRAM
  213. #undef CONFIG_CMD_I2C
  214. #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
  215. #undef CONFIG_CMD_SDRAM
  216. #undef CONFIG_CMD_I2C
  217. #else
  218. #undef CONFIG_CMD_PCI
  219. #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
  220. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  221. #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
  222. #define CONFIG_BOOTARGS "root=/dev/mtdblock2"
  223. #if defined(CONFIG_CMD_KGDB)
  224. #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
  225. #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
  226. #undef CONFIG_KGDB_NONE /* define if kgdb on something else */
  227. #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
  228. #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
  229. #endif
  230. #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
  231. #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
  232. /*
  233. * Miscellaneous configurable options
  234. */
  235. #define CONFIG_SYS_HUSH_PARSER
  236. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  237. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  238. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  239. #if defined(CONFIG_CMD_KGDB)
  240. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  241. #else
  242. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  243. #endif
  244. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  245. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  246. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  247. #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
  248. #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  249. #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
  250. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  251. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  252. #define CONFIG_SYS_FLASH_BASE 0xff800000
  253. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  254. #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
  255. #define CONFIG_SYS_FLASH_SIZE 8
  256. #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
  257. #define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
  258. #define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
  259. #define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
  260. #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  261. /*
  262. * JFFS2 partitions
  263. *
  264. * Note: fake mtd_id used, no linux mtd map file
  265. */
  266. #define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
  267. #define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
  268. #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
  269. /* this is stuff came out of the Motorola docs */
  270. #ifndef CONFIG_SYS_LOWBOOT
  271. #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
  272. #endif
  273. #define CONFIG_SYS_IMMR 0xF0000000
  274. #define CONFIG_SYS_BCSR 0xF4500000
  275. #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
  276. #define CONFIG_SYS_PCI_INT 0xF8200000
  277. #endif
  278. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  279. #define CONFIG_SYS_LSDRAM_BASE 0xFD000000
  280. #define RS232EN_1 0x02000002
  281. #define RS232EN_2 0x01000001
  282. #define FETHIEN1 0x08000008
  283. #define FETH1_RST 0x04000004
  284. #define FETHIEN2 0x10000000
  285. #define FETH2_RST 0x08000000
  286. #define BCSR_PCI_MODE 0x01000000
  287. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  288. #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
  289. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  290. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  291. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  292. #ifdef CONFIG_SYS_LOWBOOT
  293. /* PQ2FADS flash HRCW = 0x0EB4B645 */
  294. #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
  295. ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
  296. ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
  297. ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
  298. )
  299. #else
  300. /* PQ2FADS BCSR HRCW = 0x0CB23645 */
  301. #define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
  302. ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
  303. ( HRCW_BMS | HRCW_APPC10 ) |\
  304. ( HRCW_MODCK_H0101 ) \
  305. )
  306. #endif
  307. /* no slaves */
  308. #define CONFIG_SYS_HRCW_SLAVE1 0
  309. #define CONFIG_SYS_HRCW_SLAVE2 0
  310. #define CONFIG_SYS_HRCW_SLAVE3 0
  311. #define CONFIG_SYS_HRCW_SLAVE4 0
  312. #define CONFIG_SYS_HRCW_SLAVE5 0
  313. #define CONFIG_SYS_HRCW_SLAVE6 0
  314. #define CONFIG_SYS_HRCW_SLAVE7 0
  315. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  316. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  317. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  318. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  319. # define CONFIG_SYS_RAMBOOT
  320. #endif
  321. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  322. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  323. #ifdef CONFIG_BZIP2
  324. #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
  325. #else
  326. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
  327. #endif /* CONFIG_BZIP2 */
  328. #ifndef CONFIG_SYS_RAMBOOT
  329. # define CONFIG_ENV_IS_IN_FLASH 1
  330. # define CONFIG_ENV_SECT_SIZE 0x40000
  331. # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
  332. #else
  333. # define CONFIG_ENV_IS_IN_NVRAM 1
  334. # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  335. # define CONFIG_ENV_SIZE 0x200
  336. #endif /* CONFIG_SYS_RAMBOOT */
  337. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  338. #if defined(CONFIG_CMD_KGDB)
  339. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  340. #endif
  341. #define CONFIG_SYS_HID0_INIT 0
  342. #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
  343. #define CONFIG_SYS_HID2 0
  344. #define CONFIG_SYS_SYPCR 0xFFFFFFC3
  345. #define CONFIG_SYS_BCR 0x100C0000
  346. #define CONFIG_SYS_SIUMCR 0x0A200000
  347. #define CONFIG_SYS_SCCR SCCR_DFBRG01
  348. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
  349. #define CONFIG_SYS_OR0_PRELIM 0xFF800876
  350. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
  351. #define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
  352. /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
  353. #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  354. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
  355. #define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
  356. #elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
  357. #define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
  358. #define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
  359. #endif
  360. #define CONFIG_SYS_RMR RMR_CSRE
  361. #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  362. #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  363. #define CONFIG_SYS_RCCR 0
  364. #if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
  365. #undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
  366. #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
  367. #if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
  368. #define CONFIG_SYS_OR2 0xFE002EC0
  369. #define CONFIG_SYS_PSDMR 0x824B36A3
  370. #define CONFIG_SYS_PSRT 0x13
  371. #define CONFIG_SYS_LSDMR 0x828737A3
  372. #define CONFIG_SYS_LSRT 0x13
  373. #define CONFIG_SYS_MPTPR 0x2800
  374. #elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  375. #define CONFIG_SYS_OR2 0xFC002CC0
  376. #define CONFIG_SYS_PSDMR 0x834E24A3
  377. #define CONFIG_SYS_PSRT 0x13
  378. #define CONFIG_SYS_MPTPR 0x2800
  379. #else
  380. #define CONFIG_SYS_OR2 0xFF000CA0
  381. #define CONFIG_SYS_PSDMR 0x016EB452
  382. #define CONFIG_SYS_PSRT 0x21
  383. #define CONFIG_SYS_LSDMR 0x0086A522
  384. #define CONFIG_SYS_LSRT 0x21
  385. #define CONFIG_SYS_MPTPR 0x1900
  386. #endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
  387. #define CONFIG_SYS_RESET_ADDRESS 0x04400000
  388. #if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
  389. /* PCI Memory map (if different from default map */
  390. #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
  391. #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
  392. #define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
  393. PICMR_PREFETCH_EN)
  394. /*
  395. * These are the windows that allow the CPU to access PCI address space.
  396. * All three PCI master windows, which allow the CPU to access PCI
  397. * prefetch, non prefetch, and IO space (see below), must all fit within
  398. * these windows.
  399. */
  400. /*
  401. * Master window that allows the CPU to access PCI Memory (prefetch).
  402. * This window will be setup with the second set of Outbound ATU registers
  403. * in the bridge.
  404. */
  405. #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
  406. #define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
  407. #define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
  408. #define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
  409. #define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
  410. /*
  411. * Master window that allows the CPU to access PCI Memory (non-prefetch).
  412. * This window will be setup with the second set of Outbound ATU registers
  413. * in the bridge.
  414. */
  415. #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
  416. #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
  417. #define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
  418. #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
  419. #define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
  420. /*
  421. * Master window that allows the CPU to access PCI IO space.
  422. * This window will be setup with the first set of Outbound ATU registers
  423. * in the bridge.
  424. */
  425. #define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
  426. #define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
  427. #define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
  428. #define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
  429. #define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
  430. /* PCIBR0 - for PCI IO*/
  431. #define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
  432. #define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
  433. /* PCIBR1 - prefetch and non-prefetch regions joined together */
  434. #define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
  435. #define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
  436. #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
  437. #define CONFIG_HAS_ETH0
  438. #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
  439. #define CONFIG_HAS_ETH1
  440. #endif
  441. #define CONFIG_NETDEV eth0
  442. #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
  443. #define XMK_STR(x) #x
  444. #define MK_STR(x) XMK_STR(x)
  445. #define CONFIG_EXTRA_ENV_SETTINGS \
  446. "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
  447. "tftpflash=tftpboot $loadaddr $uboot; " \
  448. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  449. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  450. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  451. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  452. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  453. "fdtaddr=400000\0" \
  454. "console=ttyCPM0\0" \
  455. "setbootargs=setenv bootargs " \
  456. "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
  457. "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
  458. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  459. "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
  460. #define CONFIG_NFSBOOTCOMMAND \
  461. "setenv rootdev /dev/nfs;" \
  462. "run setipargs;" \
  463. "tftp $loadaddr $bootfile;" \
  464. "tftp $fdtaddr $fdtfile;" \
  465. "bootm $loadaddr - $fdtaddr"
  466. #define CONFIG_RAMBOOTCOMMAND \
  467. "setenv rootdev /dev/ram;" \
  468. "run setbootargs;" \
  469. "tftp $ramdiskaddr $ramdiskfile;" \
  470. "tftp $loadaddr $bootfile;" \
  471. "tftp $fdtaddr $fdtfile;" \
  472. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  473. #undef MK_STR
  474. #undef XMK_STR
  475. #endif /* __CONFIG_H */