mpc85xx.h 796 B

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  1. /*
  2. * Copyright 2004 Freescale Semiconductor.
  3. * Copyright(c) 2003 Motorola Inc.
  4. * Xianghua Xiao (x.xiao@motorola.com)
  5. */
  6. #ifndef __MPC85xx_H__
  7. #define __MPC85xx_H__
  8. #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
  9. #if defined(CONFIG_E500)
  10. #include <e500.h>
  11. #endif
  12. /*
  13. * SCCR - System Clock Control Register, 9-8
  14. */
  15. #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
  16. #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
  17. #define SCCR_DFBRG_SHIFT 0
  18. #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
  19. #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
  20. #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
  21. #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
  22. #endif /* __MPC85xx_H__ */