board.c 2.7 KB

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  1. /*
  2. * board.c
  3. *
  4. * Common board functions for AM33XX based boards
  5. *
  6. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <common.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/omap.h>
  22. #include <asm/arch/ddr_defs.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/mmc_host_def.h>
  25. #include <asm/arch/common_def.h>
  26. #include <asm/io.h>
  27. #include <asm/omap_common.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  30. struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
  31. struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  32. /* UART Defines */
  33. #ifdef CONFIG_SPL_BUILD
  34. #define UART_RESET (0x1 << 1)
  35. #define UART_CLK_RUNNING_MASK 0x1
  36. #define UART_SMART_IDLE_EN (0x1 << 0x3)
  37. #endif
  38. /*
  39. * early system init of muxing and clocks.
  40. */
  41. void s_init(void)
  42. {
  43. /* WDT1 is already running when the bootloader gets control
  44. * Disable it to avoid "random" resets
  45. */
  46. writel(0xAAAA, &wdtimer->wdtwspr);
  47. while (readl(&wdtimer->wdtwwps) != 0x0)
  48. ;
  49. writel(0x5555, &wdtimer->wdtwspr);
  50. while (readl(&wdtimer->wdtwwps) != 0x0)
  51. ;
  52. #ifdef CONFIG_SPL_BUILD
  53. /* Setup the PLLs and the clocks for the peripherals */
  54. pll_init();
  55. /* UART softreset */
  56. u32 regVal;
  57. enable_uart0_pin_mux();
  58. regVal = readl(&uart_base->uartsyscfg);
  59. regVal |= UART_RESET;
  60. writel(regVal, &uart_base->uartsyscfg);
  61. while ((readl(&uart_base->uartsyssts) &
  62. UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
  63. ;
  64. /* Disable smart idle */
  65. regVal = readl(&uart_base->uartsyscfg);
  66. regVal |= UART_SMART_IDLE_EN;
  67. writel(regVal, &uart_base->uartsyscfg);
  68. /* Initialize the Timer */
  69. init_timer();
  70. preloader_console_init();
  71. config_ddr();
  72. #endif
  73. /* Enable MMC0 */
  74. enable_mmc0_pin_mux();
  75. }
  76. /* Initialize timer */
  77. void init_timer(void)
  78. {
  79. /* Reset the Timer */
  80. writel(0x2, (&timer_base->tscir));
  81. /* Wait until the reset is done */
  82. while (readl(&timer_base->tiocp_cfg) & 1)
  83. ;
  84. /* Start the Timer */
  85. writel(0x1, (&timer_base->tclr));
  86. }
  87. #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
  88. int board_mmc_init(bd_t *bis)
  89. {
  90. return omap_mmc_init(0, 0, 0);
  91. }
  92. #endif
  93. void setup_clocks_for_console(void)
  94. {
  95. /* Not yet implemented */
  96. return;
  97. }