cpu.c 4.0 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Marius Groeger <mgroeger@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8. * Alex Zuepke <azu@sysgo.de>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. /*
  29. * CPU specific code
  30. */
  31. #include <common.h>
  32. #include <command.h>
  33. #include <asm/arch/ixp425.h>
  34. ulong loops_per_jiffy;
  35. #ifdef CONFIG_USE_IRQ
  36. DECLARE_GLOBAL_DATA_PTR;
  37. #endif
  38. #if defined(CONFIG_DISPLAY_CPUINFO)
  39. int print_cpuinfo (void)
  40. {
  41. unsigned long id;
  42. int speed = 0;
  43. asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
  44. puts("CPU: Intel IXP425 at ");
  45. switch ((id & 0x000003f0) >> 4) {
  46. case 0x1c:
  47. loops_per_jiffy = 887467;
  48. speed = 533;
  49. break;
  50. case 0x1d:
  51. loops_per_jiffy = 666016;
  52. speed = 400;
  53. break;
  54. case 0x1f:
  55. loops_per_jiffy = 442901;
  56. speed = 266;
  57. break;
  58. }
  59. if (speed)
  60. printf("%d MHz\n", speed);
  61. else
  62. puts("unknown revision\n");
  63. return 0;
  64. }
  65. #endif /* CONFIG_DISPLAY_CPUINFO */
  66. int cpu_init (void)
  67. {
  68. /*
  69. * setup up stacks if necessary
  70. */
  71. #ifdef CONFIG_USE_IRQ
  72. IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
  73. FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
  74. #endif
  75. #if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined (CONFIG_PCI)
  76. pci_init();
  77. #endif
  78. return 0;
  79. }
  80. int cleanup_before_linux (void)
  81. {
  82. /*
  83. * this function is called just before we call linux
  84. * it prepares the processor for linux
  85. *
  86. * just disable everything that can disturb booting linux
  87. */
  88. unsigned long i;
  89. disable_interrupts ();
  90. /* turn off I-cache */
  91. asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  92. i &= ~0x1000;
  93. asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
  94. /* flush I-cache */
  95. asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
  96. return (0);
  97. }
  98. int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  99. {
  100. printf ("resetting ...\n");
  101. udelay (50000); /* wait 50 ms */
  102. disable_interrupts ();
  103. reset_cpu (0);
  104. /*NOTREACHED*/
  105. return (0);
  106. }
  107. /* taken from blob */
  108. void icache_enable (void)
  109. {
  110. register u32 i;
  111. /* read control register */
  112. asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  113. /* set i-cache */
  114. i |= 0x1000;
  115. /* write back to control register */
  116. asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
  117. }
  118. void icache_disable (void)
  119. {
  120. register u32 i;
  121. /* read control register */
  122. asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  123. /* clear i-cache */
  124. i &= ~0x1000;
  125. /* write back to control register */
  126. asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
  127. /* flush i-cache */
  128. asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
  129. }
  130. int icache_status (void)
  131. {
  132. register u32 i;
  133. /* read control register */
  134. asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
  135. /* return bit */
  136. return (i & 0x1000);
  137. }
  138. /* we will never enable dcache, because we have to setup MMU first */
  139. void dcache_enable (void)
  140. {
  141. return;
  142. }
  143. void dcache_disable (void)
  144. {
  145. return;
  146. }
  147. int dcache_status (void)
  148. {
  149. return 0; /* always off */
  150. }
  151. /* FIXME */
  152. /*
  153. void pci_init(void)
  154. {
  155. return;
  156. }
  157. */
  158. #ifdef CONFIG_BOOTCOUNT_LIMIT
  159. void bootcount_store (ulong a)
  160. {
  161. volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR);
  162. save_addr[0] = a;
  163. save_addr[1] = BOOTCOUNT_MAGIC;
  164. }
  165. ulong bootcount_load (void)
  166. {
  167. volatile ulong *save_addr = (volatile ulong *)(CFG_BOOTCOUNT_ADDR);
  168. if (save_addr[1] != BOOTCOUNT_MAGIC)
  169. return 0;
  170. else
  171. return save_addr[0];
  172. }
  173. #endif /* CONFIG_BOOTCOUNT_LIMIT */