s3c_udc_otg.c 21 KB

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  1. /*
  2. * drivers/usb/gadget/s3c_udc_otg.c
  3. * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
  4. *
  5. * Copyright (C) 2008 for Samsung Electronics
  6. *
  7. * BSP Support for Samsung's UDC driver
  8. * available at:
  9. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10. *
  11. * State machine bugfixes:
  12. * Marek Szyprowski <m.szyprowski@samsung.com>
  13. *
  14. * Ported to u-boot:
  15. * Marek Szyprowski <m.szyprowski@samsung.com>
  16. * Lukasz Majewski <l.majewski@samsumg.com>
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. */
  33. #include <common.h>
  34. #include <asm/errno.h>
  35. #include <linux/list.h>
  36. #include <malloc.h>
  37. #include <linux/usb/ch9.h>
  38. #include <usbdescriptors.h>
  39. #include <linux/usb/gadget.h>
  40. #include <asm/byteorder.h>
  41. #include <asm/unaligned.h>
  42. #include <asm/io.h>
  43. #include <asm/mach-types.h>
  44. #include <asm/arch/gpio.h>
  45. #include "regs-otg.h"
  46. #include <usb/lin_gadget_compat.h>
  47. /***********************************************************/
  48. #define OTG_DMA_MODE 1
  49. #undef DEBUG_S3C_UDC_SETUP
  50. #undef DEBUG_S3C_UDC_EP0
  51. #undef DEBUG_S3C_UDC_ISR
  52. #undef DEBUG_S3C_UDC_OUT_EP
  53. #undef DEBUG_S3C_UDC_IN_EP
  54. #undef DEBUG_S3C_UDC
  55. /* #define DEBUG_S3C_UDC_SETUP */
  56. /* #define DEBUG_S3C_UDC_EP0 */
  57. /* #define DEBUG_S3C_UDC_ISR */
  58. /* #define DEBUG_S3C_UDC_OUT_EP */
  59. /* #define DEBUG_S3C_UDC_IN_EP */
  60. /* #define DEBUG_S3C_UDC */
  61. #include <usb/s3c_udc.h>
  62. #define EP0_CON 0
  63. #define EP_MASK 0xF
  64. static char *state_names[] = {
  65. "WAIT_FOR_SETUP",
  66. "DATA_STATE_XMIT",
  67. "DATA_STATE_NEED_ZLP",
  68. "WAIT_FOR_OUT_STATUS",
  69. "DATA_STATE_RECV",
  70. "WAIT_FOR_COMPLETE",
  71. "WAIT_FOR_OUT_COMPLETE",
  72. "WAIT_FOR_IN_COMPLETE",
  73. "WAIT_FOR_NULL_COMPLETE",
  74. };
  75. #define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) Samsung Electronics"
  76. #define DRIVER_VERSION "15 March 2009"
  77. struct s3c_udc *the_controller;
  78. static const char driver_name[] = "s3c-udc";
  79. static const char driver_desc[] = DRIVER_DESC;
  80. static const char ep0name[] = "ep0-control";
  81. /* Max packet size*/
  82. static unsigned int ep0_fifo_size = 64;
  83. static unsigned int ep_fifo_size = 512;
  84. static unsigned int ep_fifo_size2 = 1024;
  85. static int reset_available = 1;
  86. static struct usb_ctrlrequest *usb_ctrl;
  87. static dma_addr_t usb_ctrl_dma_addr;
  88. /*
  89. Local declarations.
  90. */
  91. static int s3c_ep_enable(struct usb_ep *ep,
  92. const struct usb_endpoint_descriptor *);
  93. static int s3c_ep_disable(struct usb_ep *ep);
  94. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  95. gfp_t gfp_flags);
  96. static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
  97. static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  98. static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
  99. static int s3c_fifo_status(struct usb_ep *ep);
  100. static void s3c_fifo_flush(struct usb_ep *ep);
  101. static void s3c_ep0_read(struct s3c_udc *dev);
  102. static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
  103. static void s3c_handle_ep0(struct s3c_udc *dev);
  104. static int s3c_ep0_write(struct s3c_udc *dev);
  105. static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req);
  106. static void done(struct s3c_ep *ep, struct s3c_request *req, int status);
  107. static void stop_activity(struct s3c_udc *dev,
  108. struct usb_gadget_driver *driver);
  109. static int udc_enable(struct s3c_udc *dev);
  110. static void udc_set_address(struct s3c_udc *dev, unsigned char address);
  111. static void reconfig_usbd(void);
  112. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
  113. static void nuke(struct s3c_ep *ep, int status);
  114. static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
  115. static void s3c_udc_set_nak(struct s3c_ep *ep);
  116. static struct usb_ep_ops s3c_ep_ops = {
  117. .enable = s3c_ep_enable,
  118. .disable = s3c_ep_disable,
  119. .alloc_request = s3c_alloc_request,
  120. .free_request = s3c_free_request,
  121. .queue = s3c_queue,
  122. .dequeue = s3c_dequeue,
  123. .set_halt = s3c_udc_set_halt,
  124. .fifo_status = s3c_fifo_status,
  125. .fifo_flush = s3c_fifo_flush,
  126. };
  127. #define create_proc_files() do {} while (0)
  128. #define remove_proc_files() do {} while (0)
  129. /***********************************************************/
  130. void __iomem *regs_otg;
  131. struct s3c_usbotg_reg *reg;
  132. struct s3c_usbotg_phy *phy;
  133. static unsigned int usb_phy_ctrl;
  134. void otg_phy_init(struct s3c_udc *dev)
  135. {
  136. dev->pdata->phy_control(1);
  137. /*USB PHY0 Enable */
  138. printf("USB PHY0 Enable\n");
  139. /* Enable PHY */
  140. writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
  141. if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
  142. writel((readl(&phy->phypwr)
  143. &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
  144. &~FORCE_SUSPEND_0), &phy->phypwr);
  145. else /* C110 GONI */
  146. writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
  147. &~FORCE_SUSPEND_0), &phy->phypwr);
  148. writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
  149. CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  150. writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
  151. | PHY_SW_RST0, &phy->rstcon);
  152. udelay(10);
  153. writel(readl(&phy->rstcon)
  154. &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
  155. udelay(10);
  156. }
  157. void otg_phy_off(struct s3c_udc *dev)
  158. {
  159. /* reset controller just in case */
  160. writel(PHY_SW_RST0, &phy->rstcon);
  161. udelay(20);
  162. writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
  163. udelay(20);
  164. writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
  165. | FORCE_SUSPEND_0, &phy->phypwr);
  166. writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
  167. writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
  168. &phy->phyclk);
  169. udelay(10000);
  170. dev->pdata->phy_control(0);
  171. }
  172. /***********************************************************/
  173. #include "s3c_udc_otg_xfer_dma.c"
  174. /*
  175. * udc_disable - disable USB device controller
  176. */
  177. static void udc_disable(struct s3c_udc *dev)
  178. {
  179. DEBUG_SETUP("%s: %p\n", __func__, dev);
  180. udc_set_address(dev, 0);
  181. dev->ep0state = WAIT_FOR_SETUP;
  182. dev->gadget.speed = USB_SPEED_UNKNOWN;
  183. dev->usb_address = 0;
  184. otg_phy_off(dev);
  185. }
  186. /*
  187. * udc_reinit - initialize software state
  188. */
  189. static void udc_reinit(struct s3c_udc *dev)
  190. {
  191. unsigned int i;
  192. DEBUG_SETUP("%s: %p\n", __func__, dev);
  193. /* device/ep0 records init */
  194. INIT_LIST_HEAD(&dev->gadget.ep_list);
  195. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  196. dev->ep0state = WAIT_FOR_SETUP;
  197. /* basic endpoint records init */
  198. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  199. struct s3c_ep *ep = &dev->ep[i];
  200. if (i != 0)
  201. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  202. ep->desc = 0;
  203. ep->stopped = 0;
  204. INIT_LIST_HEAD(&ep->queue);
  205. ep->pio_irqs = 0;
  206. }
  207. /* the rest was statically initialized, and is read-only */
  208. }
  209. #define BYTES2MAXP(x) (x / 8)
  210. #define MAXP2BYTES(x) (x * 8)
  211. /* until it's enabled, this UDC should be completely invisible
  212. * to any USB host.
  213. */
  214. static int udc_enable(struct s3c_udc *dev)
  215. {
  216. DEBUG_SETUP("%s: %p\n", __func__, dev);
  217. otg_phy_init(dev);
  218. reconfig_usbd();
  219. DEBUG_SETUP("S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  220. readl(&reg->gintmsk));
  221. dev->gadget.speed = USB_SPEED_UNKNOWN;
  222. return 0;
  223. }
  224. /*
  225. Register entry point for the peripheral controller driver.
  226. */
  227. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  228. {
  229. struct s3c_udc *dev = the_controller;
  230. int retval = 0;
  231. unsigned long flags;
  232. DEBUG_SETUP("%s: %s\n", __func__, "no name");
  233. if (!driver
  234. || (driver->speed != USB_SPEED_FULL
  235. && driver->speed != USB_SPEED_HIGH)
  236. || !driver->bind || !driver->disconnect || !driver->setup)
  237. return -EINVAL;
  238. if (!dev)
  239. return -ENODEV;
  240. if (dev->driver)
  241. return -EBUSY;
  242. spin_lock_irqsave(&dev->lock, flags);
  243. /* first hook up the driver ... */
  244. dev->driver = driver;
  245. spin_unlock_irqrestore(&dev->lock, flags);
  246. if (retval) { /* TODO */
  247. printf("target device_add failed, error %d\n", retval);
  248. return retval;
  249. }
  250. retval = driver->bind(&dev->gadget);
  251. if (retval) {
  252. DEBUG_SETUP("%s: bind to driver --> error %d\n",
  253. dev->gadget.name, retval);
  254. dev->driver = 0;
  255. return retval;
  256. }
  257. enable_irq(IRQ_OTG);
  258. DEBUG_SETUP("Registered gadget driver %s\n", dev->gadget.name);
  259. udc_enable(dev);
  260. return 0;
  261. }
  262. /*
  263. * Unregister entry point for the peripheral controller driver.
  264. */
  265. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  266. {
  267. struct s3c_udc *dev = the_controller;
  268. unsigned long flags;
  269. if (!dev)
  270. return -ENODEV;
  271. if (!driver || driver != dev->driver)
  272. return -EINVAL;
  273. spin_lock_irqsave(&dev->lock, flags);
  274. dev->driver = 0;
  275. stop_activity(dev, driver);
  276. spin_unlock_irqrestore(&dev->lock, flags);
  277. driver->unbind(&dev->gadget);
  278. disable_irq(IRQ_OTG);
  279. udc_disable(dev);
  280. return 0;
  281. }
  282. /*
  283. * done - retire a request; caller blocked irqs
  284. */
  285. static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
  286. {
  287. unsigned int stopped = ep->stopped;
  288. debug("%s: %s %p, req = %p, stopped = %d\n",
  289. __func__, ep->ep.name, ep, &req->req, stopped);
  290. list_del_init(&req->queue);
  291. if (likely(req->req.status == -EINPROGRESS))
  292. req->req.status = status;
  293. else
  294. status = req->req.status;
  295. if (status && status != -ESHUTDOWN) {
  296. debug("complete %s req %p stat %d len %u/%u\n",
  297. ep->ep.name, &req->req, status,
  298. req->req.actual, req->req.length);
  299. }
  300. /* don't modify queue heads during completion callback */
  301. ep->stopped = 1;
  302. #ifdef DEBUG_S3C_UDC
  303. printf("calling complete callback\n");
  304. {
  305. int i, len = req->req.length;
  306. printf("pkt[%d] = ", req->req.length);
  307. if (len > 64)
  308. len = 64;
  309. for (i = 0; i < len; i++) {
  310. printf("%02x", ((u8 *)req->req.buf)[i]);
  311. if ((i & 7) == 7)
  312. printf(" ");
  313. }
  314. printf("\n");
  315. }
  316. #endif
  317. spin_unlock(&ep->dev->lock);
  318. req->req.complete(&ep->ep, &req->req);
  319. spin_lock(&ep->dev->lock);
  320. debug("callback completed\n");
  321. ep->stopped = stopped;
  322. }
  323. /*
  324. * nuke - dequeue ALL requests
  325. */
  326. static void nuke(struct s3c_ep *ep, int status)
  327. {
  328. struct s3c_request *req;
  329. debug("%s: %s %p\n", __func__, ep->ep.name, ep);
  330. /* called with irqs blocked */
  331. while (!list_empty(&ep->queue)) {
  332. req = list_entry(ep->queue.next, struct s3c_request, queue);
  333. done(ep, req, status);
  334. }
  335. }
  336. static void stop_activity(struct s3c_udc *dev,
  337. struct usb_gadget_driver *driver)
  338. {
  339. int i;
  340. /* don't disconnect drivers more than once */
  341. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  342. driver = 0;
  343. dev->gadget.speed = USB_SPEED_UNKNOWN;
  344. /* prevent new request submissions, kill any outstanding requests */
  345. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  346. struct s3c_ep *ep = &dev->ep[i];
  347. ep->stopped = 1;
  348. nuke(ep, -ESHUTDOWN);
  349. }
  350. /* report disconnect; the driver is already quiesced */
  351. if (driver) {
  352. spin_unlock(&dev->lock);
  353. driver->disconnect(&dev->gadget);
  354. spin_lock(&dev->lock);
  355. }
  356. /* re-init driver-visible data structures */
  357. udc_reinit(dev);
  358. }
  359. static void reconfig_usbd(void)
  360. {
  361. /* 2. Soft-reset OTG Core and then unreset again. */
  362. int i;
  363. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  364. debug("Reseting OTG controller\n");
  365. writel(0<<15 /* PHY Low Power Clock sel*/
  366. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  367. |0x5<<10 /* Turnaround time*/
  368. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  369. /* 1:SRP enable] H1= 1,1*/
  370. |0<<7 /* Ulpi DDR sel*/
  371. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  372. |0<<4 /* 0: utmi+, 1:ulpi*/
  373. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  374. |0x7<<0, /* HS/FS Timeout**/
  375. &reg->gusbcfg);
  376. /* 3. Put the OTG device core in the disconnected state.*/
  377. uTemp = readl(&reg->dctl);
  378. uTemp |= SOFT_DISCONNECT;
  379. writel(uTemp, &reg->dctl);
  380. udelay(20);
  381. /* 4. Make the OTG device core exit from the disconnected state.*/
  382. uTemp = readl(&reg->dctl);
  383. uTemp = uTemp & ~SOFT_DISCONNECT;
  384. writel(uTemp, &reg->dctl);
  385. /* 5. Configure OTG Core to initial settings of device mode.*/
  386. /* [][1: full speed(30Mhz) 0:high speed]*/
  387. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  388. mdelay(1);
  389. /* 6. Unmask the core interrupts*/
  390. writel(GINTMSK_INIT, &reg->gintmsk);
  391. /* 7. Set NAK bit of EP0, EP1, EP2*/
  392. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  393. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  394. for (i = 1; i < S3C_MAX_ENDPOINTS; i++) {
  395. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  396. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  397. }
  398. /* 8. Unmask EPO interrupts*/
  399. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  400. | (1 << EP0_CON), &reg->daintmsk);
  401. /* 9. Unmask device OUT EP common interrupts*/
  402. writel(DOEPMSK_INIT, &reg->doepmsk);
  403. /* 10. Unmask device IN EP common interrupts*/
  404. writel(DIEPMSK_INIT, &reg->diepmsk);
  405. /* 11. Set Rx FIFO Size (in 32-bit words) */
  406. writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
  407. /* 12. Set Non Periodic Tx FIFO Size */
  408. writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
  409. &reg->gnptxfsiz);
  410. for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++)
  411. writel((PTX_FIFO_SIZE >> 2) << 16 |
  412. ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
  413. PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
  414. &reg->dieptxf[i-1]);
  415. /* Flush the RX FIFO */
  416. writel(RX_FIFO_FLUSH, &reg->grstctl);
  417. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  418. debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  419. /* Flush all the Tx FIFO's */
  420. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  421. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  422. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  423. debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  424. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  425. /* For Slave mode*/
  426. /* EP0: Control OUT */
  427. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  428. &reg->out_endp[EP0_CON].doepctl);
  429. /* 14. Initialize OTG Link Core.*/
  430. writel(GAHBCFG_INIT, &reg->gahbcfg);
  431. }
  432. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
  433. {
  434. unsigned int ep_ctrl;
  435. int i;
  436. if (speed == USB_SPEED_HIGH) {
  437. ep0_fifo_size = 64;
  438. ep_fifo_size = 512;
  439. ep_fifo_size2 = 1024;
  440. dev->gadget.speed = USB_SPEED_HIGH;
  441. } else {
  442. ep0_fifo_size = 64;
  443. ep_fifo_size = 64;
  444. ep_fifo_size2 = 64;
  445. dev->gadget.speed = USB_SPEED_FULL;
  446. }
  447. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  448. for (i = 1; i < S3C_MAX_ENDPOINTS; i++)
  449. dev->ep[i].ep.maxpacket = ep_fifo_size;
  450. /* EP0 - Control IN (64 bytes)*/
  451. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  452. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  453. /* EP0 - Control OUT (64 bytes)*/
  454. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  455. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  456. }
  457. static int s3c_ep_enable(struct usb_ep *_ep,
  458. const struct usb_endpoint_descriptor *desc)
  459. {
  460. struct s3c_ep *ep;
  461. struct s3c_udc *dev;
  462. unsigned long flags;
  463. debug("%s: %p\n", __func__, _ep);
  464. ep = container_of(_ep, struct s3c_ep, ep);
  465. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  466. || desc->bDescriptorType != USB_DT_ENDPOINT
  467. || ep->bEndpointAddress != desc->bEndpointAddress
  468. || ep_maxpacket(ep) <
  469. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  470. debug("%s: bad ep or descriptor\n", __func__);
  471. return -EINVAL;
  472. }
  473. /* xfer types must match, except that interrupt ~= bulk */
  474. if (ep->bmAttributes != desc->bmAttributes
  475. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  476. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  477. debug("%s: %s type mismatch\n", __func__, _ep->name);
  478. return -EINVAL;
  479. }
  480. /* hardware _could_ do smaller, but driver doesn't */
  481. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
  482. && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) !=
  483. ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
  484. debug("%s: bad %s maxpacket\n", __func__, _ep->name);
  485. return -ERANGE;
  486. }
  487. dev = ep->dev;
  488. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  489. debug("%s: bogus device state\n", __func__);
  490. return -ESHUTDOWN;
  491. }
  492. ep->stopped = 0;
  493. ep->desc = desc;
  494. ep->pio_irqs = 0;
  495. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  496. /* Reset halt state */
  497. s3c_udc_set_nak(ep);
  498. s3c_udc_set_halt(_ep, 0);
  499. spin_lock_irqsave(&ep->dev->lock, flags);
  500. s3c_udc_ep_activate(ep);
  501. spin_unlock_irqrestore(&ep->dev->lock, flags);
  502. debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  503. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  504. return 0;
  505. }
  506. /*
  507. * Disable EP
  508. */
  509. static int s3c_ep_disable(struct usb_ep *_ep)
  510. {
  511. struct s3c_ep *ep;
  512. unsigned long flags;
  513. debug("%s: %p\n", __func__, _ep);
  514. ep = container_of(_ep, struct s3c_ep, ep);
  515. if (!_ep || !ep->desc) {
  516. debug("%s: %s not enabled\n", __func__,
  517. _ep ? ep->ep.name : NULL);
  518. return -EINVAL;
  519. }
  520. spin_lock_irqsave(&ep->dev->lock, flags);
  521. /* Nuke all pending requests */
  522. nuke(ep, -ESHUTDOWN);
  523. ep->desc = 0;
  524. ep->stopped = 1;
  525. spin_unlock_irqrestore(&ep->dev->lock, flags);
  526. debug("%s: disabled %s\n", __func__, _ep->name);
  527. return 0;
  528. }
  529. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  530. gfp_t gfp_flags)
  531. {
  532. struct s3c_request *req;
  533. debug("%s: %s %p\n", __func__, ep->name, ep);
  534. req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
  535. if (!req)
  536. return 0;
  537. memset(req, 0, sizeof *req);
  538. INIT_LIST_HEAD(&req->queue);
  539. return &req->req;
  540. }
  541. static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
  542. {
  543. struct s3c_request *req;
  544. debug("%s: %p\n", __func__, ep);
  545. req = container_of(_req, struct s3c_request, req);
  546. WARN_ON(!list_empty(&req->queue));
  547. kfree(req);
  548. }
  549. /* dequeue JUST ONE request */
  550. static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  551. {
  552. struct s3c_ep *ep;
  553. struct s3c_request *req;
  554. unsigned long flags;
  555. debug("%s: %p\n", __func__, _ep);
  556. ep = container_of(_ep, struct s3c_ep, ep);
  557. if (!_ep || ep->ep.name == ep0name)
  558. return -EINVAL;
  559. spin_lock_irqsave(&ep->dev->lock, flags);
  560. /* make sure it's actually queued on this endpoint */
  561. list_for_each_entry(req, &ep->queue, queue) {
  562. if (&req->req == _req)
  563. break;
  564. }
  565. if (&req->req != _req) {
  566. spin_unlock_irqrestore(&ep->dev->lock, flags);
  567. return -EINVAL;
  568. }
  569. done(ep, req, -ECONNRESET);
  570. spin_unlock_irqrestore(&ep->dev->lock, flags);
  571. return 0;
  572. }
  573. /*
  574. * Return bytes in EP FIFO
  575. */
  576. static int s3c_fifo_status(struct usb_ep *_ep)
  577. {
  578. int count = 0;
  579. struct s3c_ep *ep;
  580. ep = container_of(_ep, struct s3c_ep, ep);
  581. if (!_ep) {
  582. debug("%s: bad ep\n", __func__);
  583. return -ENODEV;
  584. }
  585. debug("%s: %d\n", __func__, ep_index(ep));
  586. /* LPD can't report unclaimed bytes from IN fifos */
  587. if (ep_is_in(ep))
  588. return -EOPNOTSUPP;
  589. return count;
  590. }
  591. /*
  592. * Flush EP FIFO
  593. */
  594. static void s3c_fifo_flush(struct usb_ep *_ep)
  595. {
  596. struct s3c_ep *ep;
  597. ep = container_of(_ep, struct s3c_ep, ep);
  598. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  599. debug("%s: bad ep\n", __func__);
  600. return;
  601. }
  602. debug("%s: %d\n", __func__, ep_index(ep));
  603. }
  604. static const struct usb_gadget_ops s3c_udc_ops = {
  605. /* current versions must always be self-powered */
  606. };
  607. static struct s3c_udc memory = {
  608. .usb_address = 0,
  609. .gadget = {
  610. .ops = &s3c_udc_ops,
  611. .ep0 = &memory.ep[0].ep,
  612. .name = driver_name,
  613. },
  614. /* control endpoint */
  615. .ep[0] = {
  616. .ep = {
  617. .name = ep0name,
  618. .ops = &s3c_ep_ops,
  619. .maxpacket = EP0_FIFO_SIZE,
  620. },
  621. .dev = &memory,
  622. .bEndpointAddress = 0,
  623. .bmAttributes = 0,
  624. .ep_type = ep_control,
  625. },
  626. /* first group of endpoints */
  627. .ep[1] = {
  628. .ep = {
  629. .name = "ep1in-bulk",
  630. .ops = &s3c_ep_ops,
  631. .maxpacket = EP_FIFO_SIZE,
  632. },
  633. .dev = &memory,
  634. .bEndpointAddress = USB_DIR_IN | 1,
  635. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  636. .ep_type = ep_bulk_out,
  637. .fifo_num = 1,
  638. },
  639. .ep[2] = {
  640. .ep = {
  641. .name = "ep2out-bulk",
  642. .ops = &s3c_ep_ops,
  643. .maxpacket = EP_FIFO_SIZE,
  644. },
  645. .dev = &memory,
  646. .bEndpointAddress = USB_DIR_OUT | 2,
  647. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  648. .ep_type = ep_bulk_in,
  649. .fifo_num = 2,
  650. },
  651. .ep[3] = {
  652. .ep = {
  653. .name = "ep3in-int",
  654. .ops = &s3c_ep_ops,
  655. .maxpacket = EP_FIFO_SIZE,
  656. },
  657. .dev = &memory,
  658. .bEndpointAddress = USB_DIR_IN | 3,
  659. .bmAttributes = USB_ENDPOINT_XFER_INT,
  660. .ep_type = ep_interrupt,
  661. .fifo_num = 3,
  662. },
  663. };
  664. /*
  665. * probe - binds to the platform device
  666. */
  667. int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
  668. {
  669. struct s3c_udc *dev = &memory;
  670. int retval = 0, i;
  671. debug("%s: %p\n", __func__, pdata);
  672. dev->pdata = pdata;
  673. phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
  674. reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
  675. usb_phy_ctrl = pdata->usb_phy_ctrl;
  676. /* regs_otg = (void *)pdata->regs_otg; */
  677. dev->gadget.is_dualspeed = 1; /* Hack only*/
  678. dev->gadget.is_otg = 0;
  679. dev->gadget.is_a_peripheral = 0;
  680. dev->gadget.b_hnp_enable = 0;
  681. dev->gadget.a_hnp_support = 0;
  682. dev->gadget.a_alt_hnp_support = 0;
  683. the_controller = dev;
  684. for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
  685. dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE,
  686. DMA_BUFFER_SIZE);
  687. dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
  688. invalidate_dcache_range((unsigned long) dev->dma_buf[i],
  689. (unsigned long) (dev->dma_buf[i]
  690. + DMA_BUFFER_SIZE));
  691. }
  692. usb_ctrl = dev->dma_buf[0];
  693. usb_ctrl_dma_addr = dev->dma_addr[0];
  694. udc_reinit(dev);
  695. return retval;
  696. }
  697. int usb_gadget_handle_interrupts()
  698. {
  699. u32 intr_status = readl(&reg->gintsts);
  700. u32 gintmsk = readl(&reg->gintmsk);
  701. if (intr_status & gintmsk)
  702. return s3c_udc_irq(1, (void *)the_controller);
  703. return 0;
  704. }