pci.c 12 KB

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  1. /*
  2. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  3. * Andreas Heppel <aheppel@sysgo.de>
  4. *
  5. * (C) Copyright 2002, 2003
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * PCI routines
  28. */
  29. #include <common.h>
  30. #ifdef CONFIG_PCI
  31. #include <command.h>
  32. #include <asm/processor.h>
  33. #include <asm/io.h>
  34. #include <pci.h>
  35. #ifdef DEBUG
  36. #define DEBUGF(x...) printf(x)
  37. #else
  38. #define DEBUGF(x...)
  39. #endif /* DEBUG */
  40. /*
  41. *
  42. */
  43. #define PCI_HOSE_OP(rw, size, type) \
  44. int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
  45. pci_dev_t dev, \
  46. int offset, type value) \
  47. { \
  48. return hose->rw##_##size(hose, dev, offset, value); \
  49. }
  50. PCI_HOSE_OP(read, byte, u8 *)
  51. PCI_HOSE_OP(read, word, u16 *)
  52. PCI_HOSE_OP(read, dword, u32 *)
  53. PCI_HOSE_OP(write, byte, u8)
  54. PCI_HOSE_OP(write, word, u16)
  55. PCI_HOSE_OP(write, dword, u32)
  56. #define PCI_OP(rw, size, type, error_code) \
  57. int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
  58. { \
  59. struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
  60. \
  61. if (!hose) \
  62. { \
  63. error_code; \
  64. return -1; \
  65. } \
  66. \
  67. return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  68. }
  69. PCI_OP(read, byte, u8 *, *value = 0xff)
  70. PCI_OP(read, word, u16 *, *value = 0xffff)
  71. PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  72. PCI_OP(write, byte, u8, )
  73. PCI_OP(write, word, u16, )
  74. PCI_OP(write, dword, u32, )
  75. #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
  76. int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  77. pci_dev_t dev, \
  78. int offset, type val) \
  79. { \
  80. u32 val32; \
  81. \
  82. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  83. return -1; \
  84. \
  85. *val = (val32 >> ((offset & (int)off_mask) * 8)); \
  86. \
  87. return 0; \
  88. }
  89. #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
  90. int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  91. pci_dev_t dev, \
  92. int offset, type val) \
  93. { \
  94. u32 val32, mask, ldata; \
  95. \
  96. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  97. return -1; \
  98. \
  99. mask = val_mask; \
  100. ldata = (((unsigned long)val) & mask) << ((offset & (int)off_mask) * 8);\
  101. mask <<= ((mask & (int)off_mask) * 8); \
  102. val32 = (val32 & ~mask) | ldata; \
  103. \
  104. if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
  105. return -1; \
  106. \
  107. return 0; \
  108. }
  109. PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
  110. PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
  111. PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
  112. PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
  113. /*
  114. *
  115. */
  116. static struct pci_controller* hose_head = NULL;
  117. void pci_register_hose(struct pci_controller* hose)
  118. {
  119. struct pci_controller **phose = &hose_head;
  120. while(*phose)
  121. phose = &(*phose)->next;
  122. hose->next = NULL;
  123. *phose = hose;
  124. }
  125. struct pci_controller *pci_bus_to_hose (int bus)
  126. {
  127. struct pci_controller *hose;
  128. for (hose = hose_head; hose; hose = hose->next)
  129. if (bus >= hose->first_busno && bus <= hose->last_busno)
  130. return hose;
  131. return NULL;
  132. }
  133. pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
  134. {
  135. struct pci_controller * hose;
  136. u16 vendor, device;
  137. u8 header_type;
  138. pci_dev_t bdf;
  139. int i, bus, found_multi = 0;
  140. for (hose = hose_head; hose; hose = hose->next)
  141. {
  142. #ifdef CFG_SCSI_SCAN_BUS_REVERSE
  143. for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
  144. #else
  145. for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
  146. #endif
  147. for (bdf = PCI_BDF(bus,0,0);
  148. #ifdef CONFIG_ELPPC
  149. bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
  150. #else
  151. bdf < PCI_BDF(bus+1,0,0);
  152. #endif
  153. bdf += PCI_BDF(0,0,1))
  154. {
  155. if (!PCI_FUNC(bdf)) {
  156. pci_read_config_byte(bdf,
  157. PCI_HEADER_TYPE,
  158. &header_type);
  159. found_multi = header_type & 0x80;
  160. } else {
  161. if (!found_multi)
  162. continue;
  163. }
  164. pci_read_config_word(bdf,
  165. PCI_VENDOR_ID,
  166. &vendor);
  167. pci_read_config_word(bdf,
  168. PCI_DEVICE_ID,
  169. &device);
  170. for (i=0; ids[i].vendor != 0; i++)
  171. if (vendor == ids[i].vendor &&
  172. device == ids[i].device)
  173. {
  174. if (index <= 0)
  175. return bdf;
  176. index--;
  177. }
  178. }
  179. }
  180. return (-1);
  181. }
  182. pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
  183. {
  184. static struct pci_device_id ids[2] = {{}, {0, 0}};
  185. ids[0].vendor = vendor;
  186. ids[0].device = device;
  187. return pci_find_devices(ids, index);
  188. }
  189. /*
  190. *
  191. */
  192. unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
  193. unsigned long phys_addr,
  194. unsigned long flags)
  195. {
  196. struct pci_region *res;
  197. unsigned long bus_addr;
  198. int i;
  199. if (!hose) {
  200. printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
  201. goto Done;
  202. }
  203. for (i = 0; i < hose->region_count; i++) {
  204. res = &hose->regions[i];
  205. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  206. continue;
  207. bus_addr = phys_addr - res->phys_start + res->bus_start;
  208. if (bus_addr >= res->bus_start &&
  209. bus_addr < res->bus_start + res->size) {
  210. return bus_addr;
  211. }
  212. }
  213. printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
  214. Done:
  215. return 0;
  216. }
  217. unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
  218. unsigned long bus_addr,
  219. unsigned long flags)
  220. {
  221. struct pci_region *res;
  222. int i;
  223. if (!hose) {
  224. printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
  225. goto Done;
  226. }
  227. for (i = 0; i < hose->region_count; i++) {
  228. res = &hose->regions[i];
  229. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  230. continue;
  231. if (bus_addr >= res->bus_start &&
  232. bus_addr < res->bus_start + res->size) {
  233. return bus_addr - res->bus_start + res->phys_start;
  234. }
  235. }
  236. printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
  237. Done:
  238. return 0;
  239. }
  240. /*
  241. *
  242. */
  243. int pci_hose_config_device(struct pci_controller *hose,
  244. pci_dev_t dev,
  245. unsigned long io,
  246. unsigned long mem,
  247. unsigned long command)
  248. {
  249. unsigned int bar_response, bar_size, bar_value, old_command;
  250. unsigned char pin;
  251. int bar, found_mem64;
  252. DEBUGF ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
  253. io, mem, command);
  254. pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
  255. for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
  256. pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
  257. pci_hose_read_config_dword (hose, dev, bar, &bar_response);
  258. if (!bar_response)
  259. continue;
  260. found_mem64 = 0;
  261. /* Check the BAR type and set our address mask */
  262. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  263. bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
  264. /* round up region base address to a multiple of size */
  265. io = ((io - 1) | (bar_size - 1)) + 1;
  266. bar_value = io;
  267. /* compute new region base address */
  268. io = io + bar_size;
  269. } else {
  270. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  271. PCI_BASE_ADDRESS_MEM_TYPE_64)
  272. found_mem64 = 1;
  273. bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  274. /* round up region base address to multiple of size */
  275. mem = ((mem - 1) | (bar_size - 1)) + 1;
  276. bar_value = mem;
  277. /* compute new region base address */
  278. mem = mem + bar_size;
  279. }
  280. /* Write it out and update our limit */
  281. pci_hose_write_config_dword (hose, dev, bar, bar_value);
  282. if (found_mem64) {
  283. bar += 4;
  284. pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
  285. }
  286. }
  287. /* Configure Cache Line Size Register */
  288. pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  289. /* Configure Latency Timer */
  290. pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
  291. /* Disable interrupt line, if device says it wants to use interrupts */
  292. pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
  293. if (pin != 0) {
  294. pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
  295. }
  296. pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
  297. pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
  298. (old_command & 0xffff0000) | command);
  299. return 0;
  300. }
  301. /*
  302. *
  303. */
  304. struct pci_config_table *pci_find_config(struct pci_controller *hose,
  305. unsigned short class,
  306. unsigned int vendor,
  307. unsigned int device,
  308. unsigned int bus,
  309. unsigned int dev,
  310. unsigned int func)
  311. {
  312. struct pci_config_table *table;
  313. for (table = hose->config_table; table && table->vendor; table++) {
  314. if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
  315. (table->device == PCI_ANY_ID || table->device == device) &&
  316. (table->class == PCI_ANY_ID || table->class == class) &&
  317. (table->bus == PCI_ANY_ID || table->bus == bus) &&
  318. (table->dev == PCI_ANY_ID || table->dev == dev) &&
  319. (table->func == PCI_ANY_ID || table->func == func)) {
  320. return table;
  321. }
  322. }
  323. return NULL;
  324. }
  325. void pci_cfgfunc_config_device(struct pci_controller *hose,
  326. pci_dev_t dev,
  327. struct pci_config_table *entry)
  328. {
  329. pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
  330. }
  331. void pci_cfgfunc_do_nothing(struct pci_controller *hose,
  332. pci_dev_t dev, struct pci_config_table *entry)
  333. {
  334. }
  335. /*
  336. *
  337. */
  338. /* HJF: Changed this to return int. I think this is required
  339. * to get the correct result when scanning bridges
  340. */
  341. extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
  342. extern void pciauto_config_init(struct pci_controller *hose);
  343. int pci_hose_scan_bus(struct pci_controller *hose, int bus)
  344. {
  345. unsigned int sub_bus, found_multi=0;
  346. unsigned short vendor, device, class;
  347. unsigned char header_type;
  348. struct pci_config_table *cfg;
  349. pci_dev_t dev;
  350. sub_bus = bus;
  351. for (dev = PCI_BDF(bus,0,0);
  352. dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
  353. dev += PCI_BDF(0,0,1))
  354. {
  355. /* Skip our host bridge */
  356. if ( dev == PCI_BDF(hose->first_busno,0,0) )
  357. continue;
  358. if (PCI_FUNC(dev) && !found_multi)
  359. continue;
  360. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
  361. pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
  362. if (vendor != 0xffff && vendor != 0x0000) {
  363. if (!PCI_FUNC(dev))
  364. found_multi = header_type & 0x80;
  365. DEBUGF("PCI Scan: Found Bus %d, Device %d, Function %d\n",
  366. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
  367. pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
  368. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  369. cfg = pci_find_config(hose, class, vendor, device,
  370. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  371. if (cfg) {
  372. cfg->config_device(hose, dev, cfg);
  373. #ifdef CONFIG_PCI_PNP
  374. } else {
  375. int n = pciauto_config_device(hose, dev);
  376. sub_bus = max(sub_bus, n);
  377. #endif
  378. }
  379. if (hose->fixup_irq)
  380. hose->fixup_irq(hose, dev);
  381. #ifdef CONFIG_PCI_SCAN_SHOW
  382. /* Skip our host bridge */
  383. if ( dev != PCI_BDF(hose->first_busno,0,0) ) {
  384. unsigned char int_line;
  385. pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
  386. &int_line);
  387. printf(" %02x %02x %04x %04x %04x %02x\n",
  388. PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
  389. int_line);
  390. }
  391. #endif
  392. }
  393. }
  394. return sub_bus;
  395. }
  396. int pci_hose_scan(struct pci_controller *hose)
  397. {
  398. #ifdef CONFIG_PCI_PNP
  399. pciauto_config_init(hose);
  400. #endif
  401. return pci_hose_scan_bus(hose, hose->first_busno);
  402. }
  403. void pci_init(void)
  404. {
  405. #if defined(CONFIG_PCI_BOOTDELAY)
  406. char *s;
  407. int i;
  408. /* wait "pcidelay" ms (if defined)... */
  409. s = getenv ("pcidelay");
  410. if (s) {
  411. int val = simple_strtoul (s, NULL, 10);
  412. for (i=0; i<val; i++)
  413. udelay (1000);
  414. }
  415. #endif /* CONFIG_PCI_BOOTDELAY */
  416. /* now call board specific pci_init()... */
  417. pci_init_board();
  418. }
  419. #endif /* CONFIG_PCI */