evm.c 4.2 KB

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  1. /*
  2. * (C) Copyright 2004-2008
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Author :
  6. * Manikandan Pillai <mani.pillai@ti.com>
  7. *
  8. * Derived from Beagle Board and 3430 SDP code by
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <khasim@ti.com>
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #include <common.h>
  31. #include <netdev.h>
  32. #include <asm/io.h>
  33. #include <asm/arch/mem.h>
  34. #include <asm/arch/mux.h>
  35. #include <asm/arch/sys_proto.h>
  36. #include <i2c.h>
  37. #include <asm/mach-types.h>
  38. #include "evm.h"
  39. static u8 omap3_evm_version;
  40. u8 get_omap3_evm_rev(void)
  41. {
  42. return omap3_evm_version;
  43. }
  44. static void omap3_evm_get_revision(void)
  45. {
  46. unsigned int smsc_id;
  47. /* Ethernet PHY ID is stored at ID_REV register */
  48. smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
  49. printf("Read back SMSC id 0x%x\n", smsc_id);
  50. switch (smsc_id) {
  51. /* SMSC9115 chipset */
  52. case 0x01150000:
  53. omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
  54. break;
  55. /* SMSC 9220 chipset */
  56. case 0x92200000:
  57. default:
  58. omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
  59. }
  60. }
  61. /*
  62. * Routine: board_init
  63. * Description: Early hardware init.
  64. */
  65. int board_init(void)
  66. {
  67. DECLARE_GLOBAL_DATA_PTR;
  68. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  69. /* board id for Linux */
  70. gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
  71. /* boot param addr */
  72. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  73. return 0;
  74. }
  75. /*
  76. * Routine: misc_init_r
  77. * Description: Init ethernet (done here so udelay works)
  78. */
  79. int misc_init_r(void)
  80. {
  81. #ifdef CONFIG_DRIVER_OMAP34XX_I2C
  82. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  83. #endif
  84. #if defined(CONFIG_CMD_NET)
  85. setup_net_chip();
  86. #endif
  87. dieid_num_r();
  88. return 0;
  89. }
  90. /*
  91. * Routine: set_muxconf_regs
  92. * Description: Setting up the configuration Mux registers specific to the
  93. * hardware. Many pins need to be moved from protect to primary
  94. * mode.
  95. */
  96. void set_muxconf_regs(void)
  97. {
  98. MUX_EVM();
  99. }
  100. /*
  101. * Routine: setup_net_chip
  102. * Description: Setting up the configuration GPMC registers specific to the
  103. * Ethernet hardware.
  104. */
  105. static void setup_net_chip(void)
  106. {
  107. struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
  108. struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  109. /* Configure GPMC registers */
  110. writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
  111. writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
  112. writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
  113. writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
  114. writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
  115. writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
  116. writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
  117. /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
  118. writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
  119. /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
  120. writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
  121. /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
  122. writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
  123. &ctrl_base->gpmc_nadv_ale);
  124. /* Make GPIO 64 as output pin */
  125. writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
  126. /* Now send a pulse on the GPIO pin */
  127. writel(GPIO0, &gpio3_base->setdataout);
  128. udelay(1);
  129. writel(GPIO0, &gpio3_base->cleardataout);
  130. udelay(1);
  131. writel(GPIO0, &gpio3_base->setdataout);
  132. /* determine omap3evm revision */
  133. omap3_evm_get_revision();
  134. }
  135. int board_eth_init(bd_t *bis)
  136. {
  137. int rc = 0;
  138. #ifdef CONFIG_SMC911X
  139. rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  140. #endif
  141. return rc;
  142. }