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uboot-vybrid_public
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uboot-vybrid_pu...
/
include
/
405gp_i2c.h

405gp_i2c.h 2.2 KB
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  1. #ifndef _405gp_i2c_h_
    2. 

  2. #define _405gp_i2c_h_
    3. 

  3. 

  4. #define	   I2C_REGISTERS_BASE_ADDRESS 0xEF600500
    5. 

  5. #define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
    6. 

  6. #define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
    7. 

  7. #define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
    8. 

  8. #define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
    9. 

  9. #define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
    10. 

  10. #define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
    11. 

  11. #define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
    12. 

  12. #define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
    13. 

  13. #define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
    14. 

  14. #define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
    15. 

  15. #define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
    16. 

  16. #define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
    17. 

  17. #define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
    18. 

  18. #define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
    19. 

  19. #define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
    20. 

  20. 

  21. /* MDCNTL Register Bit definition */
    22. 

  22. #define    IIC_MDCNTL_HSCL 0x01
    23. 

  23. #define    IIC_MDCNTL_EUBS 0x02
    24. 

  24. #define    IIC_MDCNTL_EINT 0x04
    25. 

  25. #define    IIC_MDCNTL_ESM  0x08
    26. 

  26. #define    IIC_MDCNTL_FSM  0x10
    27. 

  27. #define    IIC_MDCNTL_EGC  0x20
    28. 

  28. #define    IIC_MDCNTL_FMDB 0x40
    29. 

  29. #define    IIC_MDCNTL_FSDB 0x80
    30. 

  30. 

  31. /* CNTL Register Bit definition */
    32. 

  32. #define    IIC_CNTL_PT     0x01
    33. 

  33. #define    IIC_CNTL_READ   0x02
    34. 

  34. #define    IIC_CNTL_CHT    0x04
    35. 

  35. #define    IIC_CNTL_RPST   0x08
    36. 

  36. /* bit 2/3 for Transfer count*/
    37. 

  37. #define    IIC_CNTL_AMD    0x40
    38. 

  38. #define    IIC_CNTL_HMT    0x80
    39. 

  39. 

  40. /* STS Register Bit definition */
    41. 

  41. #define    IIC_STS_PT	   0X01
    42. 

  42. #define    IIC_STS_IRQA    0x02
    43. 

  43. #define    IIC_STS_ERR	   0X04
    44. 

  44. #define    IIC_STS_SCMP    0x08
    45. 

  45. #define    IIC_STS_MDBF    0x10
    46. 

  46. #define    IIC_STS_MDBS    0X20
    47. 

  47. #define    IIC_STS_SLPR    0x40
    48. 

  48. #define    IIC_STS_SSS     0x80
    49. 

  49. 

  50. /* EXTSTS Register Bit definition */
    51. 

  51. #define    IIC_EXTSTS_XFRA 0X01
    52. 

  52. #define    IIC_EXTSTS_ICT  0X02
    53. 

  53. #define    IIC_EXTSTS_LA   0X04
    54. 

  54. 

  55. /* XTCNTLSS Register Bit definition */
    56. 

  56. #define    IIC_XTCNTLSS_SRST  0x01
    57. 

  57. #define    IIC_XTCNTLSS_EPI   0x02
    58. 

  58. #define    IIC_XTCNTLSS_SDBF  0x04
    59. 

  59. #define    IIC_XTCNTLSS_SBDD  0x08
    60. 

  60. #define    IIC_XTCNTLSS_SWS   0x10
    61. 

  61. #define    IIC_XTCNTLSS_SWC   0x20
    62. 

  62. #define    IIC_XTCNTLSS_SRS   0x40
    63. 

  63. #define    IIC_XTCNTLSS_SRC   0x80
    64. 

  64. #endif
    65.