da850_pinmux.c 5.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187
  1. /*
  2. * Pinmux configurations for the DA850 SoCs
  3. *
  4. * Copyright (C) 2011 OMICRON electronics GmbH
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <common.h>
  21. #include <asm/arch/davinci_misc.h>
  22. #include <asm/arch/hardware.h>
  23. #include <asm/arch/pinmux_defs.h>
  24. /* SPI pin muxer settings */
  25. const struct pinmux_config spi1_pins_base[] = {
  26. { pinmux(5), 1, 2 }, /* SPI1_CLK */
  27. { pinmux(5), 1, 4 }, /* SPI1_SOMI */
  28. { pinmux(5), 1, 5 }, /* SPI1_SIMO */
  29. };
  30. const struct pinmux_config spi1_pins_scs0[] = {
  31. { pinmux(5), 1, 1 }, /* SPI1_SCS[0] */
  32. };
  33. /* UART pin muxer settings */
  34. const struct pinmux_config uart0_pins_txrx[] = {
  35. { pinmux(3), 2, 4 }, /* UART0_RXD */
  36. { pinmux(3), 2, 5 }, /* UART0_TXD */
  37. };
  38. const struct pinmux_config uart1_pins_txrx[] = {
  39. { pinmux(4), 2, 6 }, /* UART1_RXD */
  40. { pinmux(4), 2, 7 }, /* UART1_TXD */
  41. };
  42. const struct pinmux_config uart2_pins_txrx[] = {
  43. { pinmux(4), 2, 4 }, /* UART2_RXD */
  44. { pinmux(4), 2, 5 }, /* UART2_TXD */
  45. };
  46. const struct pinmux_config uart2_pins_rtscts[] = {
  47. { pinmux(0), 4, 6 }, /* UART2_RTS */
  48. { pinmux(0), 4, 7 }, /* UART2_CTS */
  49. };
  50. /* EMAC pin muxer settings*/
  51. const struct pinmux_config emac_pins_rmii[] = {
  52. { pinmux(14), 8, 2 }, /* RMII_TXD[1] */
  53. { pinmux(14), 8, 3 }, /* RMII_TXD[0] */
  54. { pinmux(14), 8, 4 }, /* RMII_TXEN */
  55. { pinmux(14), 8, 5 }, /* RMII_RXD[1] */
  56. { pinmux(14), 8, 6 }, /* RMII_RXD[0] */
  57. { pinmux(14), 8, 7 }, /* RMII_RXER */
  58. { pinmux(15), 8, 1 }, /* RMII_CRS_DV */
  59. };
  60. const struct pinmux_config emac_pins_mii[] = {
  61. { pinmux(2), 8, 1 }, /* MII_TXEN */
  62. { pinmux(2), 8, 2 }, /* MII_TXCLK */
  63. { pinmux(2), 8, 3 }, /* MII_COL */
  64. { pinmux(2), 8, 4 }, /* MII_TXD[3] */
  65. { pinmux(2), 8, 5 }, /* MII_TXD[2] */
  66. { pinmux(2), 8, 6 }, /* MII_TXD[1] */
  67. { pinmux(2), 8, 7 }, /* MII_TXD[0] */
  68. { pinmux(3), 8, 0 }, /* MII_RXCLK */
  69. { pinmux(3), 8, 1 }, /* MII_RXDV */
  70. { pinmux(3), 8, 2 }, /* MII_RXER */
  71. { pinmux(3), 8, 3 }, /* MII_CRS */
  72. { pinmux(3), 8, 4 }, /* MII_RXD[3] */
  73. { pinmux(3), 8, 5 }, /* MII_RXD[2] */
  74. { pinmux(3), 8, 6 }, /* MII_RXD[1] */
  75. { pinmux(3), 8, 7 }, /* MII_RXD[0] */
  76. };
  77. const struct pinmux_config emac_pins_mdio[] = {
  78. { pinmux(4), 8, 0 }, /* MDIO_CLK */
  79. { pinmux(4), 8, 1 }, /* MDIO_D */
  80. };
  81. /* I2C pin muxer settings */
  82. const struct pinmux_config i2c0_pins[] = {
  83. { pinmux(4), 2, 2 }, /* I2C0_SCL */
  84. { pinmux(4), 2, 3 }, /* I2C0_SDA */
  85. };
  86. const struct pinmux_config i2c1_pins[] = {
  87. { pinmux(4), 4, 4 }, /* I2C1_SCL */
  88. { pinmux(4), 4, 5 }, /* I2C1_SDA */
  89. };
  90. /* EMIFA pin muxer settings */
  91. const struct pinmux_config emifa_pins_cs2[] = {
  92. { pinmux(7), 1, 0 }, /* EMA_CS2 */
  93. };
  94. const struct pinmux_config emifa_pins_cs3[] = {
  95. { pinmux(7), 1, 1 }, /* EMA_CS[3] */
  96. };
  97. const struct pinmux_config emifa_pins_cs4[] = {
  98. { pinmux(7), 1, 2 }, /* EMA_CS[4] */
  99. };
  100. const struct pinmux_config emifa_pins_nand[] = {
  101. { pinmux(7), 1, 4 }, /* EMA_WE */
  102. { pinmux(7), 1, 5 }, /* EMA_OE */
  103. { pinmux(9), 1, 0 }, /* EMA_D[7] */
  104. { pinmux(9), 1, 1 }, /* EMA_D[6] */
  105. { pinmux(9), 1, 2 }, /* EMA_D[5] */
  106. { pinmux(9), 1, 3 }, /* EMA_D[4] */
  107. { pinmux(9), 1, 4 }, /* EMA_D[3] */
  108. { pinmux(9), 1, 5 }, /* EMA_D[2] */
  109. { pinmux(9), 1, 6 }, /* EMA_D[1] */
  110. { pinmux(9), 1, 7 }, /* EMA_D[0] */
  111. { pinmux(12), 1, 5 }, /* EMA_A[2] */
  112. { pinmux(12), 1, 6 }, /* EMA_A[1] */
  113. };
  114. /* NOR pin muxer settings */
  115. const struct pinmux_config emifa_pins_nor[] = {
  116. { pinmux(5), 1, 6 }, /* EMA_BA[1] */
  117. { pinmux(6), 1, 6 }, /* EMA_WAIT[1] */
  118. { pinmux(7), 1, 4 }, /* EMA_WE */
  119. { pinmux(7), 1, 5 }, /* EMA_OE */
  120. { pinmux(8), 1, 0 }, /* EMA_D[15] */
  121. { pinmux(8), 1, 1 }, /* EMA_D[14] */
  122. { pinmux(8), 1, 2 }, /* EMA_D[13] */
  123. { pinmux(8), 1, 3 }, /* EMA_D[12] */
  124. { pinmux(8), 1, 4 }, /* EMA_D[11] */
  125. { pinmux(8), 1, 5 }, /* EMA_D[10] */
  126. { pinmux(8), 1, 6 }, /* EMA_D[9] */
  127. { pinmux(8), 1, 7 }, /* EMA_D[8] */
  128. { pinmux(9), 1, 0 }, /* EMA_D[7] */
  129. { pinmux(9), 1, 1 }, /* EMA_D[6] */
  130. { pinmux(9), 1, 2 }, /* EMA_D[5] */
  131. { pinmux(9), 1, 3 }, /* EMA_D[4] */
  132. { pinmux(9), 1, 4 }, /* EMA_D[3] */
  133. { pinmux(9), 1, 5 }, /* EMA_D[2] */
  134. { pinmux(9), 1, 6 }, /* EMA_D[1] */
  135. { pinmux(9), 1, 7 }, /* EMA_D[0] */
  136. { pinmux(10), 1, 1 }, /* EMA_A[22] */
  137. { pinmux(10), 1, 2 }, /* EMA_A[21] */
  138. { pinmux(10), 1, 3 }, /* EMA_A[20] */
  139. { pinmux(10), 1, 4 }, /* EMA_A[19] */
  140. { pinmux(10), 1, 5 }, /* EMA_A[18] */
  141. { pinmux(10), 1, 6 }, /* EMA_A[17] */
  142. { pinmux(10), 1, 7 }, /* EMA_A[16] */
  143. { pinmux(11), 1, 0 }, /* EMA_A[15] */
  144. { pinmux(11), 1, 1 }, /* EMA_A[14] */
  145. { pinmux(11), 1, 2 }, /* EMA_A[13] */
  146. { pinmux(11), 1, 3 }, /* EMA_A[12] */
  147. { pinmux(11), 1, 4 }, /* EMA_A[11] */
  148. { pinmux(11), 1, 5 }, /* EMA_A[10] */
  149. { pinmux(11), 1, 6 }, /* EMA_A[9] */
  150. { pinmux(11), 1, 7 }, /* EMA_A[8] */
  151. { pinmux(12), 1, 0 }, /* EMA_A[7] */
  152. { pinmux(12), 1, 1 }, /* EMA_A[6] */
  153. { pinmux(12), 1, 2 }, /* EMA_A[5] */
  154. { pinmux(12), 1, 3 }, /* EMA_A[4] */
  155. { pinmux(12), 1, 4 }, /* EMA_A[3] */
  156. { pinmux(12), 1, 5 }, /* EMA_A[2] */
  157. { pinmux(12), 1, 6 }, /* EMA_A[1] */
  158. { pinmux(12), 1, 7 }, /* EMA_A[0] */
  159. };
  160. /* MMC0 pin muxer settings */
  161. const struct pinmux_config mmc0_pins[] = {
  162. { pinmux(10), 2, 0 }, /* MMCSD0_CLK */
  163. { pinmux(10), 2, 1 }, /* MMCSD0_CMD */
  164. { pinmux(10), 2, 2 }, /* MMCSD0_DAT_0 */
  165. { pinmux(10), 2, 3 }, /* MMCSD0_DAT_1 */
  166. { pinmux(10), 2, 4 }, /* MMCSD0_DAT_2 */
  167. { pinmux(10), 2, 5 }, /* MMCSD0_DAT_3 */
  168. /* DA850 supports only 4-bit mode, remaining pins are not configured */
  169. };