Trent Piepho f62fb99941 Fix all linker script to handle all rodata sections 16 anni fa
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Makefile 0e7927db13 FSL DDR: Convert STXSSA to new DDR code. 16 anni fa
config.mk ee1529838a Add support for STX GP3SSA (stxssa) Board with 4 MiB flash. 18 anni fa
ddr.c b4983e16d1 fsl-ddr: use the 1T timing as default configuration 16 anni fa
law.c 6d0f6bcf33 rename CFG_ macros to CONFIG_SYS 16 anni fa
stxssa.c 6d0f6bcf33 rename CFG_ macros to CONFIG_SYS 16 anni fa
tlb.c 6d0f6bcf33 rename CFG_ macros to CONFIG_SYS 16 anni fa
u-boot.lds f62fb99941 Fix all linker script to handle all rodata sections 16 anni fa