s3c_udc_otg.c 21 KB

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  1. /*
  2. * drivers/usb/gadget/s3c_udc_otg.c
  3. * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
  4. *
  5. * Copyright (C) 2008 for Samsung Electronics
  6. *
  7. * BSP Support for Samsung's UDC driver
  8. * available at:
  9. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10. *
  11. * State machine bugfixes:
  12. * Marek Szyprowski <m.szyprowski@samsung.com>
  13. *
  14. * Ported to u-boot:
  15. * Marek Szyprowski <m.szyprowski@samsung.com>
  16. * Lukasz Majewski <l.majewski@samsumg.com>
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. */
  33. #include <common.h>
  34. #include <asm/errno.h>
  35. #include <linux/list.h>
  36. #include <malloc.h>
  37. #include <linux/usb/ch9.h>
  38. #include <linux/usb/gadget.h>
  39. #include <asm/byteorder.h>
  40. #include <asm/unaligned.h>
  41. #include <asm/io.h>
  42. #include <asm/mach-types.h>
  43. #include <asm/arch/gpio.h>
  44. #include "regs-otg.h"
  45. #include <usb/s3c_udc.h>
  46. #include <usb/lin_gadget_compat.h>
  47. /***********************************************************/
  48. #define OTG_DMA_MODE 1
  49. #undef DEBUG_S3C_UDC_SETUP
  50. #undef DEBUG_S3C_UDC_EP0
  51. #undef DEBUG_S3C_UDC_ISR
  52. #undef DEBUG_S3C_UDC_OUT_EP
  53. #undef DEBUG_S3C_UDC_IN_EP
  54. #undef DEBUG_S3C_UDC
  55. /* #define DEBUG_S3C_UDC_SETUP */
  56. /* #define DEBUG_S3C_UDC_EP0 */
  57. /* #define DEBUG_S3C_UDC_ISR */
  58. /* #define DEBUG_S3C_UDC_OUT_EP */
  59. /* #define DEBUG_S3C_UDC_IN_EP */
  60. /* #define DEBUG_S3C_UDC */
  61. #include <usb/s3c_udc.h>
  62. #define EP0_CON 0
  63. #define EP_MASK 0xF
  64. #if defined(DEBUG_S3C_UDC_SETUP) || defined(DEBUG_S3C_UDC_ISR) \
  65. || defined(DEBUG_S3C_UDC_OUT_EP)
  66. static char *state_names[] = {
  67. "WAIT_FOR_SETUP",
  68. "DATA_STATE_XMIT",
  69. "DATA_STATE_NEED_ZLP",
  70. "WAIT_FOR_OUT_STATUS",
  71. "DATA_STATE_RECV",
  72. "WAIT_FOR_COMPLETE",
  73. "WAIT_FOR_OUT_COMPLETE",
  74. "WAIT_FOR_IN_COMPLETE",
  75. "WAIT_FOR_NULL_COMPLETE",
  76. };
  77. #endif
  78. #define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) Samsung Electronics"
  79. #define DRIVER_VERSION "15 March 2009"
  80. struct s3c_udc *the_controller;
  81. static const char driver_name[] = "s3c-udc";
  82. static const char driver_desc[] = DRIVER_DESC;
  83. static const char ep0name[] = "ep0-control";
  84. /* Max packet size*/
  85. static unsigned int ep0_fifo_size = 64;
  86. static unsigned int ep_fifo_size = 512;
  87. static unsigned int ep_fifo_size2 = 1024;
  88. static int reset_available = 1;
  89. static struct usb_ctrlrequest *usb_ctrl;
  90. static dma_addr_t usb_ctrl_dma_addr;
  91. /*
  92. Local declarations.
  93. */
  94. static int s3c_ep_enable(struct usb_ep *ep,
  95. const struct usb_endpoint_descriptor *);
  96. static int s3c_ep_disable(struct usb_ep *ep);
  97. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  98. gfp_t gfp_flags);
  99. static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
  100. static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  101. static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
  102. static int s3c_fifo_status(struct usb_ep *ep);
  103. static void s3c_fifo_flush(struct usb_ep *ep);
  104. static void s3c_ep0_read(struct s3c_udc *dev);
  105. static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
  106. static void s3c_handle_ep0(struct s3c_udc *dev);
  107. static int s3c_ep0_write(struct s3c_udc *dev);
  108. static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req);
  109. static void done(struct s3c_ep *ep, struct s3c_request *req, int status);
  110. static void stop_activity(struct s3c_udc *dev,
  111. struct usb_gadget_driver *driver);
  112. static int udc_enable(struct s3c_udc *dev);
  113. static void udc_set_address(struct s3c_udc *dev, unsigned char address);
  114. static void reconfig_usbd(void);
  115. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
  116. static void nuke(struct s3c_ep *ep, int status);
  117. static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
  118. static void s3c_udc_set_nak(struct s3c_ep *ep);
  119. static struct usb_ep_ops s3c_ep_ops = {
  120. .enable = s3c_ep_enable,
  121. .disable = s3c_ep_disable,
  122. .alloc_request = s3c_alloc_request,
  123. .free_request = s3c_free_request,
  124. .queue = s3c_queue,
  125. .dequeue = s3c_dequeue,
  126. .set_halt = s3c_udc_set_halt,
  127. .fifo_status = s3c_fifo_status,
  128. .fifo_flush = s3c_fifo_flush,
  129. };
  130. #define create_proc_files() do {} while (0)
  131. #define remove_proc_files() do {} while (0)
  132. /***********************************************************/
  133. void __iomem *regs_otg;
  134. struct s3c_usbotg_reg *reg;
  135. struct s3c_usbotg_phy *phy;
  136. static unsigned int usb_phy_ctrl;
  137. void otg_phy_init(struct s3c_udc *dev)
  138. {
  139. dev->pdata->phy_control(1);
  140. /*USB PHY0 Enable */
  141. printf("USB PHY0 Enable\n");
  142. /* Enable PHY */
  143. writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
  144. if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
  145. writel((readl(&phy->phypwr)
  146. &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
  147. &~FORCE_SUSPEND_0), &phy->phypwr);
  148. else /* C110 GONI */
  149. writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
  150. &~FORCE_SUSPEND_0), &phy->phypwr);
  151. writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
  152. CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  153. writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
  154. | PHY_SW_RST0, &phy->rstcon);
  155. udelay(10);
  156. writel(readl(&phy->rstcon)
  157. &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
  158. udelay(10);
  159. }
  160. void otg_phy_off(struct s3c_udc *dev)
  161. {
  162. /* reset controller just in case */
  163. writel(PHY_SW_RST0, &phy->rstcon);
  164. udelay(20);
  165. writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
  166. udelay(20);
  167. writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
  168. | FORCE_SUSPEND_0, &phy->phypwr);
  169. writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
  170. writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
  171. &phy->phyclk);
  172. udelay(10000);
  173. dev->pdata->phy_control(0);
  174. }
  175. /***********************************************************/
  176. #include "s3c_udc_otg_xfer_dma.c"
  177. /*
  178. * udc_disable - disable USB device controller
  179. */
  180. static void udc_disable(struct s3c_udc *dev)
  181. {
  182. DEBUG_SETUP("%s: %p\n", __func__, dev);
  183. udc_set_address(dev, 0);
  184. dev->ep0state = WAIT_FOR_SETUP;
  185. dev->gadget.speed = USB_SPEED_UNKNOWN;
  186. dev->usb_address = 0;
  187. otg_phy_off(dev);
  188. }
  189. /*
  190. * udc_reinit - initialize software state
  191. */
  192. static void udc_reinit(struct s3c_udc *dev)
  193. {
  194. unsigned int i;
  195. DEBUG_SETUP("%s: %p\n", __func__, dev);
  196. /* device/ep0 records init */
  197. INIT_LIST_HEAD(&dev->gadget.ep_list);
  198. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  199. dev->ep0state = WAIT_FOR_SETUP;
  200. /* basic endpoint records init */
  201. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  202. struct s3c_ep *ep = &dev->ep[i];
  203. if (i != 0)
  204. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  205. ep->desc = 0;
  206. ep->stopped = 0;
  207. INIT_LIST_HEAD(&ep->queue);
  208. ep->pio_irqs = 0;
  209. }
  210. /* the rest was statically initialized, and is read-only */
  211. }
  212. #define BYTES2MAXP(x) (x / 8)
  213. #define MAXP2BYTES(x) (x * 8)
  214. /* until it's enabled, this UDC should be completely invisible
  215. * to any USB host.
  216. */
  217. static int udc_enable(struct s3c_udc *dev)
  218. {
  219. DEBUG_SETUP("%s: %p\n", __func__, dev);
  220. otg_phy_init(dev);
  221. reconfig_usbd();
  222. DEBUG_SETUP("S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  223. readl(&reg->gintmsk));
  224. dev->gadget.speed = USB_SPEED_UNKNOWN;
  225. return 0;
  226. }
  227. /*
  228. Register entry point for the peripheral controller driver.
  229. */
  230. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  231. {
  232. struct s3c_udc *dev = the_controller;
  233. int retval = 0;
  234. unsigned long flags;
  235. DEBUG_SETUP("%s: %s\n", __func__, "no name");
  236. if (!driver
  237. || (driver->speed != USB_SPEED_FULL
  238. && driver->speed != USB_SPEED_HIGH)
  239. || !driver->bind || !driver->disconnect || !driver->setup)
  240. return -EINVAL;
  241. if (!dev)
  242. return -ENODEV;
  243. if (dev->driver)
  244. return -EBUSY;
  245. spin_lock_irqsave(&dev->lock, flags);
  246. /* first hook up the driver ... */
  247. dev->driver = driver;
  248. spin_unlock_irqrestore(&dev->lock, flags);
  249. if (retval) { /* TODO */
  250. printf("target device_add failed, error %d\n", retval);
  251. return retval;
  252. }
  253. retval = driver->bind(&dev->gadget);
  254. if (retval) {
  255. DEBUG_SETUP("%s: bind to driver --> error %d\n",
  256. dev->gadget.name, retval);
  257. dev->driver = 0;
  258. return retval;
  259. }
  260. enable_irq(IRQ_OTG);
  261. DEBUG_SETUP("Registered gadget driver %s\n", dev->gadget.name);
  262. udc_enable(dev);
  263. return 0;
  264. }
  265. /*
  266. * Unregister entry point for the peripheral controller driver.
  267. */
  268. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  269. {
  270. struct s3c_udc *dev = the_controller;
  271. unsigned long flags;
  272. if (!dev)
  273. return -ENODEV;
  274. if (!driver || driver != dev->driver)
  275. return -EINVAL;
  276. spin_lock_irqsave(&dev->lock, flags);
  277. dev->driver = 0;
  278. stop_activity(dev, driver);
  279. spin_unlock_irqrestore(&dev->lock, flags);
  280. driver->unbind(&dev->gadget);
  281. disable_irq(IRQ_OTG);
  282. udc_disable(dev);
  283. return 0;
  284. }
  285. /*
  286. * done - retire a request; caller blocked irqs
  287. */
  288. static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
  289. {
  290. unsigned int stopped = ep->stopped;
  291. DEBUG("%s: %s %p, req = %p, stopped = %d\n",
  292. __func__, ep->ep.name, ep, &req->req, stopped);
  293. list_del_init(&req->queue);
  294. if (likely(req->req.status == -EINPROGRESS))
  295. req->req.status = status;
  296. else
  297. status = req->req.status;
  298. if (status && status != -ESHUTDOWN) {
  299. DEBUG("complete %s req %p stat %d len %u/%u\n",
  300. ep->ep.name, &req->req, status,
  301. req->req.actual, req->req.length);
  302. }
  303. /* don't modify queue heads during completion callback */
  304. ep->stopped = 1;
  305. #ifdef DEBUG_S3C_UDC
  306. printf("calling complete callback\n");
  307. {
  308. int i, len = req->req.length;
  309. printf("pkt[%d] = ", req->req.length);
  310. if (len > 64)
  311. len = 64;
  312. for (i = 0; i < len; i++) {
  313. printf("%02x", ((u8 *)req->req.buf)[i]);
  314. if ((i & 7) == 7)
  315. printf(" ");
  316. }
  317. printf("\n");
  318. }
  319. #endif
  320. spin_unlock(&ep->dev->lock);
  321. req->req.complete(&ep->ep, &req->req);
  322. spin_lock(&ep->dev->lock);
  323. DEBUG("callback completed\n");
  324. ep->stopped = stopped;
  325. }
  326. /*
  327. * nuke - dequeue ALL requests
  328. */
  329. static void nuke(struct s3c_ep *ep, int status)
  330. {
  331. struct s3c_request *req;
  332. DEBUG("%s: %s %p\n", __func__, ep->ep.name, ep);
  333. /* called with irqs blocked */
  334. while (!list_empty(&ep->queue)) {
  335. req = list_entry(ep->queue.next, struct s3c_request, queue);
  336. done(ep, req, status);
  337. }
  338. }
  339. static void stop_activity(struct s3c_udc *dev,
  340. struct usb_gadget_driver *driver)
  341. {
  342. int i;
  343. /* don't disconnect drivers more than once */
  344. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  345. driver = 0;
  346. dev->gadget.speed = USB_SPEED_UNKNOWN;
  347. /* prevent new request submissions, kill any outstanding requests */
  348. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  349. struct s3c_ep *ep = &dev->ep[i];
  350. ep->stopped = 1;
  351. nuke(ep, -ESHUTDOWN);
  352. }
  353. /* report disconnect; the driver is already quiesced */
  354. if (driver) {
  355. spin_unlock(&dev->lock);
  356. driver->disconnect(&dev->gadget);
  357. spin_lock(&dev->lock);
  358. }
  359. /* re-init driver-visible data structures */
  360. udc_reinit(dev);
  361. }
  362. static void reconfig_usbd(void)
  363. {
  364. /* 2. Soft-reset OTG Core and then unreset again. */
  365. int i;
  366. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  367. DEBUG(2, "Reseting OTG controller\n");
  368. writel(0<<15 /* PHY Low Power Clock sel*/
  369. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  370. |0x5<<10 /* Turnaround time*/
  371. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  372. /* 1:SRP enable] H1= 1,1*/
  373. |0<<7 /* Ulpi DDR sel*/
  374. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  375. |0<<4 /* 0: utmi+, 1:ulpi*/
  376. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  377. |0x7<<0, /* HS/FS Timeout**/
  378. &reg->gusbcfg);
  379. /* 3. Put the OTG device core in the disconnected state.*/
  380. uTemp = readl(&reg->dctl);
  381. uTemp |= SOFT_DISCONNECT;
  382. writel(uTemp, &reg->dctl);
  383. udelay(20);
  384. /* 4. Make the OTG device core exit from the disconnected state.*/
  385. uTemp = readl(&reg->dctl);
  386. uTemp = uTemp & ~SOFT_DISCONNECT;
  387. writel(uTemp, &reg->dctl);
  388. /* 5. Configure OTG Core to initial settings of device mode.*/
  389. /* [][1: full speed(30Mhz) 0:high speed]*/
  390. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  391. mdelay(1);
  392. /* 6. Unmask the core interrupts*/
  393. writel(GINTMSK_INIT, &reg->gintmsk);
  394. /* 7. Set NAK bit of EP0, EP1, EP2*/
  395. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  396. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  397. for (i = 1; i < S3C_MAX_ENDPOINTS; i++) {
  398. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  399. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  400. }
  401. /* 8. Unmask EPO interrupts*/
  402. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  403. | (1 << EP0_CON), &reg->daintmsk);
  404. /* 9. Unmask device OUT EP common interrupts*/
  405. writel(DOEPMSK_INIT, &reg->doepmsk);
  406. /* 10. Unmask device IN EP common interrupts*/
  407. writel(DIEPMSK_INIT, &reg->diepmsk);
  408. /* 11. Set Rx FIFO Size (in 32-bit words) */
  409. writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
  410. /* 12. Set Non Periodic Tx FIFO Size */
  411. writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
  412. &reg->gnptxfsiz);
  413. for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++)
  414. writel((PTX_FIFO_SIZE >> 2) << 16 |
  415. ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
  416. PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
  417. &reg->dieptxf[i-1]);
  418. /* Flush the RX FIFO */
  419. writel(RX_FIFO_FLUSH, &reg->grstctl);
  420. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  421. DEBUG("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  422. /* Flush all the Tx FIFO's */
  423. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  424. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  425. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  426. DEBUG("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  427. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  428. /* For Slave mode*/
  429. /* EP0: Control OUT */
  430. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  431. &reg->out_endp[EP0_CON].doepctl);
  432. /* 14. Initialize OTG Link Core.*/
  433. writel(GAHBCFG_INIT, &reg->gahbcfg);
  434. }
  435. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
  436. {
  437. unsigned int ep_ctrl;
  438. int i;
  439. if (speed == USB_SPEED_HIGH) {
  440. ep0_fifo_size = 64;
  441. ep_fifo_size = 512;
  442. ep_fifo_size2 = 1024;
  443. dev->gadget.speed = USB_SPEED_HIGH;
  444. } else {
  445. ep0_fifo_size = 64;
  446. ep_fifo_size = 64;
  447. ep_fifo_size2 = 64;
  448. dev->gadget.speed = USB_SPEED_FULL;
  449. }
  450. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  451. for (i = 1; i < S3C_MAX_ENDPOINTS; i++)
  452. dev->ep[i].ep.maxpacket = ep_fifo_size;
  453. /* EP0 - Control IN (64 bytes)*/
  454. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  455. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  456. /* EP0 - Control OUT (64 bytes)*/
  457. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  458. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  459. }
  460. static int s3c_ep_enable(struct usb_ep *_ep,
  461. const struct usb_endpoint_descriptor *desc)
  462. {
  463. struct s3c_ep *ep;
  464. struct s3c_udc *dev;
  465. unsigned long flags;
  466. DEBUG("%s: %p\n", __func__, _ep);
  467. ep = container_of(_ep, struct s3c_ep, ep);
  468. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  469. || desc->bDescriptorType != USB_DT_ENDPOINT
  470. || ep->bEndpointAddress != desc->bEndpointAddress
  471. || ep_maxpacket(ep) <
  472. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  473. DEBUG("%s: bad ep or descriptor\n", __func__);
  474. return -EINVAL;
  475. }
  476. /* xfer types must match, except that interrupt ~= bulk */
  477. if (ep->bmAttributes != desc->bmAttributes
  478. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  479. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  480. DEBUG("%s: %s type mismatch\n", __func__, _ep->name);
  481. return -EINVAL;
  482. }
  483. /* hardware _could_ do smaller, but driver doesn't */
  484. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
  485. && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) !=
  486. ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
  487. DEBUG("%s: bad %s maxpacket\n", __func__, _ep->name);
  488. return -ERANGE;
  489. }
  490. dev = ep->dev;
  491. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  492. DEBUG("%s: bogus device state\n", __func__);
  493. return -ESHUTDOWN;
  494. }
  495. ep->stopped = 0;
  496. ep->desc = desc;
  497. ep->pio_irqs = 0;
  498. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  499. /* Reset halt state */
  500. s3c_udc_set_nak(ep);
  501. s3c_udc_set_halt(_ep, 0);
  502. spin_lock_irqsave(&ep->dev->lock, flags);
  503. s3c_udc_ep_activate(ep);
  504. spin_unlock_irqrestore(&ep->dev->lock, flags);
  505. DEBUG("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  506. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  507. return 0;
  508. }
  509. /*
  510. * Disable EP
  511. */
  512. static int s3c_ep_disable(struct usb_ep *_ep)
  513. {
  514. struct s3c_ep *ep;
  515. unsigned long flags;
  516. DEBUG("%s: %p\n", __func__, _ep);
  517. ep = container_of(_ep, struct s3c_ep, ep);
  518. if (!_ep || !ep->desc) {
  519. DEBUG("%s: %s not enabled\n", __func__,
  520. _ep ? ep->ep.name : NULL);
  521. return -EINVAL;
  522. }
  523. spin_lock_irqsave(&ep->dev->lock, flags);
  524. /* Nuke all pending requests */
  525. nuke(ep, -ESHUTDOWN);
  526. ep->desc = 0;
  527. ep->stopped = 1;
  528. spin_unlock_irqrestore(&ep->dev->lock, flags);
  529. DEBUG("%s: disabled %s\n", __func__, _ep->name);
  530. return 0;
  531. }
  532. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  533. gfp_t gfp_flags)
  534. {
  535. struct s3c_request *req;
  536. DEBUG("%s: %s %p\n", __func__, ep->name, ep);
  537. req = kmalloc(sizeof *req, gfp_flags);
  538. if (!req)
  539. return 0;
  540. memset(req, 0, sizeof *req);
  541. INIT_LIST_HEAD(&req->queue);
  542. return &req->req;
  543. }
  544. static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
  545. {
  546. struct s3c_request *req;
  547. DEBUG("%s: %p\n", __func__, ep);
  548. req = container_of(_req, struct s3c_request, req);
  549. WARN_ON(!list_empty(&req->queue));
  550. kfree(req);
  551. }
  552. /* dequeue JUST ONE request */
  553. static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  554. {
  555. struct s3c_ep *ep;
  556. struct s3c_request *req;
  557. unsigned long flags;
  558. DEBUG("%s: %p\n", __func__, _ep);
  559. ep = container_of(_ep, struct s3c_ep, ep);
  560. if (!_ep || ep->ep.name == ep0name)
  561. return -EINVAL;
  562. spin_lock_irqsave(&ep->dev->lock, flags);
  563. /* make sure it's actually queued on this endpoint */
  564. list_for_each_entry(req, &ep->queue, queue) {
  565. if (&req->req == _req)
  566. break;
  567. }
  568. if (&req->req != _req) {
  569. spin_unlock_irqrestore(&ep->dev->lock, flags);
  570. return -EINVAL;
  571. }
  572. done(ep, req, -ECONNRESET);
  573. spin_unlock_irqrestore(&ep->dev->lock, flags);
  574. return 0;
  575. }
  576. /*
  577. * Return bytes in EP FIFO
  578. */
  579. static int s3c_fifo_status(struct usb_ep *_ep)
  580. {
  581. int count = 0;
  582. struct s3c_ep *ep;
  583. ep = container_of(_ep, struct s3c_ep, ep);
  584. if (!_ep) {
  585. DEBUG("%s: bad ep\n", __func__);
  586. return -ENODEV;
  587. }
  588. DEBUG("%s: %d\n", __func__, ep_index(ep));
  589. /* LPD can't report unclaimed bytes from IN fifos */
  590. if (ep_is_in(ep))
  591. return -EOPNOTSUPP;
  592. return count;
  593. }
  594. /*
  595. * Flush EP FIFO
  596. */
  597. static void s3c_fifo_flush(struct usb_ep *_ep)
  598. {
  599. struct s3c_ep *ep;
  600. ep = container_of(_ep, struct s3c_ep, ep);
  601. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  602. DEBUG("%s: bad ep\n", __func__);
  603. return;
  604. }
  605. DEBUG("%s: %d\n", __func__, ep_index(ep));
  606. }
  607. static const struct usb_gadget_ops s3c_udc_ops = {
  608. /* current versions must always be self-powered */
  609. };
  610. static struct s3c_udc memory = {
  611. .usb_address = 0,
  612. .gadget = {
  613. .ops = &s3c_udc_ops,
  614. .ep0 = &memory.ep[0].ep,
  615. .name = driver_name,
  616. },
  617. /* control endpoint */
  618. .ep[0] = {
  619. .ep = {
  620. .name = ep0name,
  621. .ops = &s3c_ep_ops,
  622. .maxpacket = EP0_FIFO_SIZE,
  623. },
  624. .dev = &memory,
  625. .bEndpointAddress = 0,
  626. .bmAttributes = 0,
  627. .ep_type = ep_control,
  628. },
  629. /* first group of endpoints */
  630. .ep[1] = {
  631. .ep = {
  632. .name = "ep1in-bulk",
  633. .ops = &s3c_ep_ops,
  634. .maxpacket = EP_FIFO_SIZE,
  635. },
  636. .dev = &memory,
  637. .bEndpointAddress = USB_DIR_IN | 1,
  638. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  639. .ep_type = ep_bulk_out,
  640. .fifo_num = 1,
  641. },
  642. .ep[2] = {
  643. .ep = {
  644. .name = "ep2out-bulk",
  645. .ops = &s3c_ep_ops,
  646. .maxpacket = EP_FIFO_SIZE,
  647. },
  648. .dev = &memory,
  649. .bEndpointAddress = USB_DIR_OUT | 2,
  650. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  651. .ep_type = ep_bulk_in,
  652. .fifo_num = 2,
  653. },
  654. .ep[3] = {
  655. .ep = {
  656. .name = "ep3in-int",
  657. .ops = &s3c_ep_ops,
  658. .maxpacket = EP_FIFO_SIZE,
  659. },
  660. .dev = &memory,
  661. .bEndpointAddress = USB_DIR_IN | 3,
  662. .bmAttributes = USB_ENDPOINT_XFER_INT,
  663. .ep_type = ep_interrupt,
  664. .fifo_num = 3,
  665. },
  666. };
  667. /*
  668. * probe - binds to the platform device
  669. */
  670. int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
  671. {
  672. struct s3c_udc *dev = &memory;
  673. int retval = 0, i;
  674. DEBUG("%s: %p\n", __func__, pdata);
  675. dev->pdata = pdata;
  676. phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
  677. reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
  678. usb_phy_ctrl = pdata->usb_phy_ctrl;
  679. /* regs_otg = (void *)pdata->regs_otg; */
  680. dev->gadget.is_dualspeed = 1; /* Hack only*/
  681. dev->gadget.is_otg = 0;
  682. dev->gadget.is_a_peripheral = 0;
  683. dev->gadget.b_hnp_enable = 0;
  684. dev->gadget.a_hnp_support = 0;
  685. dev->gadget.a_alt_hnp_support = 0;
  686. the_controller = dev;
  687. for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
  688. dev->dma_buf[i] = kmalloc(DMA_BUFFER_SIZE, GFP_KERNEL);
  689. dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
  690. invalidate_dcache_range((unsigned long) dev->dma_buf[i],
  691. (unsigned long) (dev->dma_buf[i]
  692. + DMA_BUFFER_SIZE));
  693. }
  694. usb_ctrl = dev->dma_buf[0];
  695. usb_ctrl_dma_addr = dev->dma_addr[0];
  696. udc_reinit(dev);
  697. return retval;
  698. }
  699. int usb_gadget_handle_interrupts()
  700. {
  701. u32 intr_status = readl(&reg->gintsts);
  702. u32 gintmsk = readl(&reg->gintmsk);
  703. if (intr_status & gintmsk)
  704. return s3c_udc_irq(1, (void *)the_controller);
  705. return 0;
  706. }