s3c_udc_otg.c 21 KB

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  1. /*
  2. * drivers/usb/gadget/s3c_udc_otg.c
  3. * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
  4. *
  5. * Copyright (C) 2008 for Samsung Electronics
  6. *
  7. * BSP Support for Samsung's UDC driver
  8. * available at:
  9. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10. *
  11. * State machine bugfixes:
  12. * Marek Szyprowski <m.szyprowski@samsung.com>
  13. *
  14. * Ported to u-boot:
  15. * Marek Szyprowski <m.szyprowski@samsung.com>
  16. * Lukasz Majewski <l.majewski@samsumg.com>
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. */
  33. #include <common.h>
  34. #include <asm/errno.h>
  35. #include <linux/list.h>
  36. #include <malloc.h>
  37. #include <linux/usb/ch9.h>
  38. #include <linux/usb/gadget.h>
  39. #include <asm/byteorder.h>
  40. #include <asm/io.h>
  41. #include <asm/mach-types.h>
  42. #include <asm/arch/gpio.h>
  43. #include "regs-otg.h"
  44. #include <usb/s3c_udc.h>
  45. #include <usb/lin_gadget_compat.h>
  46. /***********************************************************/
  47. #define OTG_DMA_MODE 1
  48. #undef DEBUG_S3C_UDC_SETUP
  49. #undef DEBUG_S3C_UDC_EP0
  50. #undef DEBUG_S3C_UDC_ISR
  51. #undef DEBUG_S3C_UDC_OUT_EP
  52. #undef DEBUG_S3C_UDC_IN_EP
  53. #undef DEBUG_S3C_UDC
  54. /* #define DEBUG_S3C_UDC_SETUP */
  55. /* #define DEBUG_S3C_UDC_EP0 */
  56. /* #define DEBUG_S3C_UDC_ISR */
  57. /* #define DEBUG_S3C_UDC_OUT_EP */
  58. /* #define DEBUG_S3C_UDC_IN_EP */
  59. /* #define DEBUG_S3C_UDC */
  60. #include <usb/s3c_udc.h>
  61. #define EP0_CON 0
  62. #define EP_MASK 0xF
  63. #if defined(DEBUG_S3C_UDC_SETUP) || defined(DEBUG_S3C_UDC_ISR) \
  64. || defined(DEBUG_S3C_UDC_OUT_EP)
  65. static char *state_names[] = {
  66. "WAIT_FOR_SETUP",
  67. "DATA_STATE_XMIT",
  68. "DATA_STATE_NEED_ZLP",
  69. "WAIT_FOR_OUT_STATUS",
  70. "DATA_STATE_RECV",
  71. "WAIT_FOR_COMPLETE",
  72. "WAIT_FOR_OUT_COMPLETE",
  73. "WAIT_FOR_IN_COMPLETE",
  74. "WAIT_FOR_NULL_COMPLETE",
  75. };
  76. #endif
  77. #define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) Samsung Electronics"
  78. #define DRIVER_VERSION "15 March 2009"
  79. struct s3c_udc *the_controller;
  80. static const char driver_name[] = "s3c-udc";
  81. static const char driver_desc[] = DRIVER_DESC;
  82. static const char ep0name[] = "ep0-control";
  83. /* Max packet size*/
  84. static unsigned int ep0_fifo_size = 64;
  85. static unsigned int ep_fifo_size = 512;
  86. static unsigned int ep_fifo_size2 = 1024;
  87. static int reset_available = 1;
  88. static struct usb_ctrlrequest *usb_ctrl;
  89. static dma_addr_t usb_ctrl_dma_addr;
  90. /*
  91. Local declarations.
  92. */
  93. static int s3c_ep_enable(struct usb_ep *ep,
  94. const struct usb_endpoint_descriptor *);
  95. static int s3c_ep_disable(struct usb_ep *ep);
  96. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  97. gfp_t gfp_flags);
  98. static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
  99. static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  100. static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
  101. static int s3c_fifo_status(struct usb_ep *ep);
  102. static void s3c_fifo_flush(struct usb_ep *ep);
  103. static void s3c_ep0_read(struct s3c_udc *dev);
  104. static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
  105. static void s3c_handle_ep0(struct s3c_udc *dev);
  106. static int s3c_ep0_write(struct s3c_udc *dev);
  107. static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req);
  108. static void done(struct s3c_ep *ep, struct s3c_request *req, int status);
  109. static void stop_activity(struct s3c_udc *dev,
  110. struct usb_gadget_driver *driver);
  111. static int udc_enable(struct s3c_udc *dev);
  112. static void udc_set_address(struct s3c_udc *dev, unsigned char address);
  113. static void reconfig_usbd(void);
  114. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
  115. static void nuke(struct s3c_ep *ep, int status);
  116. static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
  117. static void s3c_udc_set_nak(struct s3c_ep *ep);
  118. static struct usb_ep_ops s3c_ep_ops = {
  119. .enable = s3c_ep_enable,
  120. .disable = s3c_ep_disable,
  121. .alloc_request = s3c_alloc_request,
  122. .free_request = s3c_free_request,
  123. .queue = s3c_queue,
  124. .dequeue = s3c_dequeue,
  125. .set_halt = s3c_udc_set_halt,
  126. .fifo_status = s3c_fifo_status,
  127. .fifo_flush = s3c_fifo_flush,
  128. };
  129. #define create_proc_files() do {} while (0)
  130. #define remove_proc_files() do {} while (0)
  131. /***********************************************************/
  132. void __iomem *regs_otg;
  133. struct s3c_usbotg_reg *reg;
  134. struct s3c_usbotg_phy *phy;
  135. static unsigned int usb_phy_ctrl;
  136. void otg_phy_init(struct s3c_udc *dev)
  137. {
  138. dev->pdata->phy_control(1);
  139. /*USB PHY0 Enable */
  140. printf("USB PHY0 Enable\n");
  141. /* Enable PHY */
  142. writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
  143. if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
  144. writel((readl(&phy->phypwr)
  145. &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
  146. &~FORCE_SUSPEND_0), &phy->phypwr);
  147. else /* C110 GONI */
  148. writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
  149. &~FORCE_SUSPEND_0), &phy->phypwr);
  150. writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
  151. CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  152. writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
  153. | PHY_SW_RST0, &phy->rstcon);
  154. udelay(10);
  155. writel(readl(&phy->rstcon)
  156. &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
  157. udelay(10);
  158. }
  159. void otg_phy_off(struct s3c_udc *dev)
  160. {
  161. /* reset controller just in case */
  162. writel(PHY_SW_RST0, &phy->rstcon);
  163. udelay(20);
  164. writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
  165. udelay(20);
  166. writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
  167. | FORCE_SUSPEND_0, &phy->phypwr);
  168. writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
  169. writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
  170. &phy->phyclk);
  171. udelay(10000);
  172. dev->pdata->phy_control(0);
  173. }
  174. /***********************************************************/
  175. #include "s3c_udc_otg_xfer_dma.c"
  176. /*
  177. * udc_disable - disable USB device controller
  178. */
  179. static void udc_disable(struct s3c_udc *dev)
  180. {
  181. DEBUG_SETUP("%s: %p\n", __func__, dev);
  182. udc_set_address(dev, 0);
  183. dev->ep0state = WAIT_FOR_SETUP;
  184. dev->gadget.speed = USB_SPEED_UNKNOWN;
  185. dev->usb_address = 0;
  186. otg_phy_off(dev);
  187. }
  188. /*
  189. * udc_reinit - initialize software state
  190. */
  191. static void udc_reinit(struct s3c_udc *dev)
  192. {
  193. unsigned int i;
  194. DEBUG_SETUP("%s: %p\n", __func__, dev);
  195. /* device/ep0 records init */
  196. INIT_LIST_HEAD(&dev->gadget.ep_list);
  197. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  198. dev->ep0state = WAIT_FOR_SETUP;
  199. /* basic endpoint records init */
  200. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  201. struct s3c_ep *ep = &dev->ep[i];
  202. if (i != 0)
  203. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  204. ep->desc = 0;
  205. ep->stopped = 0;
  206. INIT_LIST_HEAD(&ep->queue);
  207. ep->pio_irqs = 0;
  208. }
  209. /* the rest was statically initialized, and is read-only */
  210. }
  211. #define BYTES2MAXP(x) (x / 8)
  212. #define MAXP2BYTES(x) (x * 8)
  213. /* until it's enabled, this UDC should be completely invisible
  214. * to any USB host.
  215. */
  216. static int udc_enable(struct s3c_udc *dev)
  217. {
  218. DEBUG_SETUP("%s: %p\n", __func__, dev);
  219. otg_phy_init(dev);
  220. reconfig_usbd();
  221. DEBUG_SETUP("S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  222. readl(&reg->gintmsk));
  223. dev->gadget.speed = USB_SPEED_UNKNOWN;
  224. return 0;
  225. }
  226. /*
  227. Register entry point for the peripheral controller driver.
  228. */
  229. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  230. {
  231. struct s3c_udc *dev = the_controller;
  232. int retval = 0;
  233. unsigned long flags;
  234. DEBUG_SETUP("%s: %s\n", __func__, "no name");
  235. if (!driver
  236. || (driver->speed != USB_SPEED_FULL
  237. && driver->speed != USB_SPEED_HIGH)
  238. || !driver->bind || !driver->disconnect || !driver->setup)
  239. return -EINVAL;
  240. if (!dev)
  241. return -ENODEV;
  242. if (dev->driver)
  243. return -EBUSY;
  244. spin_lock_irqsave(&dev->lock, flags);
  245. /* first hook up the driver ... */
  246. dev->driver = driver;
  247. spin_unlock_irqrestore(&dev->lock, flags);
  248. if (retval) { /* TODO */
  249. printf("target device_add failed, error %d\n", retval);
  250. return retval;
  251. }
  252. retval = driver->bind(&dev->gadget);
  253. if (retval) {
  254. DEBUG_SETUP("%s: bind to driver --> error %d\n",
  255. dev->gadget.name, retval);
  256. dev->driver = 0;
  257. return retval;
  258. }
  259. enable_irq(IRQ_OTG);
  260. DEBUG_SETUP("Registered gadget driver %s\n", dev->gadget.name);
  261. udc_enable(dev);
  262. return 0;
  263. }
  264. /*
  265. * Unregister entry point for the peripheral controller driver.
  266. */
  267. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  268. {
  269. struct s3c_udc *dev = the_controller;
  270. unsigned long flags;
  271. if (!dev)
  272. return -ENODEV;
  273. if (!driver || driver != dev->driver)
  274. return -EINVAL;
  275. spin_lock_irqsave(&dev->lock, flags);
  276. dev->driver = 0;
  277. stop_activity(dev, driver);
  278. spin_unlock_irqrestore(&dev->lock, flags);
  279. driver->unbind(&dev->gadget);
  280. disable_irq(IRQ_OTG);
  281. udc_disable(dev);
  282. return 0;
  283. }
  284. /*
  285. * done - retire a request; caller blocked irqs
  286. */
  287. static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
  288. {
  289. unsigned int stopped = ep->stopped;
  290. DEBUG("%s: %s %p, req = %p, stopped = %d\n",
  291. __func__, ep->ep.name, ep, &req->req, stopped);
  292. list_del_init(&req->queue);
  293. if (likely(req->req.status == -EINPROGRESS))
  294. req->req.status = status;
  295. else
  296. status = req->req.status;
  297. if (status && status != -ESHUTDOWN) {
  298. DEBUG("complete %s req %p stat %d len %u/%u\n",
  299. ep->ep.name, &req->req, status,
  300. req->req.actual, req->req.length);
  301. }
  302. /* don't modify queue heads during completion callback */
  303. ep->stopped = 1;
  304. #ifdef DEBUG_S3C_UDC
  305. printf("calling complete callback\n");
  306. {
  307. int i, len = req->req.length;
  308. printf("pkt[%d] = ", req->req.length);
  309. if (len > 64)
  310. len = 64;
  311. for (i = 0; i < len; i++) {
  312. printf("%02x", ((u8 *)req->req.buf)[i]);
  313. if ((i & 7) == 7)
  314. printf(" ");
  315. }
  316. printf("\n");
  317. }
  318. #endif
  319. spin_unlock(&ep->dev->lock);
  320. req->req.complete(&ep->ep, &req->req);
  321. spin_lock(&ep->dev->lock);
  322. DEBUG("callback completed\n");
  323. ep->stopped = stopped;
  324. }
  325. /*
  326. * nuke - dequeue ALL requests
  327. */
  328. static void nuke(struct s3c_ep *ep, int status)
  329. {
  330. struct s3c_request *req;
  331. DEBUG("%s: %s %p\n", __func__, ep->ep.name, ep);
  332. /* called with irqs blocked */
  333. while (!list_empty(&ep->queue)) {
  334. req = list_entry(ep->queue.next, struct s3c_request, queue);
  335. done(ep, req, status);
  336. }
  337. }
  338. static void stop_activity(struct s3c_udc *dev,
  339. struct usb_gadget_driver *driver)
  340. {
  341. int i;
  342. /* don't disconnect drivers more than once */
  343. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  344. driver = 0;
  345. dev->gadget.speed = USB_SPEED_UNKNOWN;
  346. /* prevent new request submissions, kill any outstanding requests */
  347. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  348. struct s3c_ep *ep = &dev->ep[i];
  349. ep->stopped = 1;
  350. nuke(ep, -ESHUTDOWN);
  351. }
  352. /* report disconnect; the driver is already quiesced */
  353. if (driver) {
  354. spin_unlock(&dev->lock);
  355. driver->disconnect(&dev->gadget);
  356. spin_lock(&dev->lock);
  357. }
  358. /* re-init driver-visible data structures */
  359. udc_reinit(dev);
  360. }
  361. static void reconfig_usbd(void)
  362. {
  363. /* 2. Soft-reset OTG Core and then unreset again. */
  364. int i;
  365. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  366. DEBUG(2, "Reseting OTG controller\n");
  367. writel(0<<15 /* PHY Low Power Clock sel*/
  368. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  369. |0x5<<10 /* Turnaround time*/
  370. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  371. /* 1:SRP enable] H1= 1,1*/
  372. |0<<7 /* Ulpi DDR sel*/
  373. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  374. |0<<4 /* 0: utmi+, 1:ulpi*/
  375. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  376. |0x7<<0, /* HS/FS Timeout**/
  377. &reg->gusbcfg);
  378. /* 3. Put the OTG device core in the disconnected state.*/
  379. uTemp = readl(&reg->dctl);
  380. uTemp |= SOFT_DISCONNECT;
  381. writel(uTemp, &reg->dctl);
  382. udelay(20);
  383. /* 4. Make the OTG device core exit from the disconnected state.*/
  384. uTemp = readl(&reg->dctl);
  385. uTemp = uTemp & ~SOFT_DISCONNECT;
  386. writel(uTemp, &reg->dctl);
  387. /* 5. Configure OTG Core to initial settings of device mode.*/
  388. /* [][1: full speed(30Mhz) 0:high speed]*/
  389. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  390. mdelay(1);
  391. /* 6. Unmask the core interrupts*/
  392. writel(GINTMSK_INIT, &reg->gintmsk);
  393. /* 7. Set NAK bit of EP0, EP1, EP2*/
  394. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  395. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  396. for (i = 1; i < S3C_MAX_ENDPOINTS; i++) {
  397. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  398. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  399. }
  400. /* 8. Unmask EPO interrupts*/
  401. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  402. | (1 << EP0_CON), &reg->daintmsk);
  403. /* 9. Unmask device OUT EP common interrupts*/
  404. writel(DOEPMSK_INIT, &reg->doepmsk);
  405. /* 10. Unmask device IN EP common interrupts*/
  406. writel(DIEPMSK_INIT, &reg->diepmsk);
  407. /* 11. Set Rx FIFO Size (in 32-bit words) */
  408. writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
  409. /* 12. Set Non Periodic Tx FIFO Size */
  410. writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
  411. &reg->gnptxfsiz);
  412. for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++)
  413. writel((PTX_FIFO_SIZE >> 2) << 16 |
  414. ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
  415. PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
  416. &reg->dieptxf[i-1]);
  417. /* Flush the RX FIFO */
  418. writel(RX_FIFO_FLUSH, &reg->grstctl);
  419. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  420. DEBUG("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  421. /* Flush all the Tx FIFO's */
  422. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  423. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  424. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  425. DEBUG("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  426. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  427. /* For Slave mode*/
  428. /* EP0: Control OUT */
  429. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  430. &reg->out_endp[EP0_CON].doepctl);
  431. /* 14. Initialize OTG Link Core.*/
  432. writel(GAHBCFG_INIT, &reg->gahbcfg);
  433. }
  434. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
  435. {
  436. unsigned int ep_ctrl;
  437. int i;
  438. if (speed == USB_SPEED_HIGH) {
  439. ep0_fifo_size = 64;
  440. ep_fifo_size = 512;
  441. ep_fifo_size2 = 1024;
  442. dev->gadget.speed = USB_SPEED_HIGH;
  443. } else {
  444. ep0_fifo_size = 64;
  445. ep_fifo_size = 64;
  446. ep_fifo_size2 = 64;
  447. dev->gadget.speed = USB_SPEED_FULL;
  448. }
  449. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  450. for (i = 1; i < S3C_MAX_ENDPOINTS; i++)
  451. dev->ep[i].ep.maxpacket = ep_fifo_size;
  452. /* EP0 - Control IN (64 bytes)*/
  453. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  454. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  455. /* EP0 - Control OUT (64 bytes)*/
  456. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  457. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  458. }
  459. static int s3c_ep_enable(struct usb_ep *_ep,
  460. const struct usb_endpoint_descriptor *desc)
  461. {
  462. struct s3c_ep *ep;
  463. struct s3c_udc *dev;
  464. unsigned long flags;
  465. DEBUG("%s: %p\n", __func__, _ep);
  466. ep = container_of(_ep, struct s3c_ep, ep);
  467. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  468. || desc->bDescriptorType != USB_DT_ENDPOINT
  469. || ep->bEndpointAddress != desc->bEndpointAddress
  470. || ep_maxpacket(ep) < le16_to_cpu(desc->wMaxPacketSize)) {
  471. DEBUG("%s: bad ep or descriptor\n", __func__);
  472. return -EINVAL;
  473. }
  474. /* xfer types must match, except that interrupt ~= bulk */
  475. if (ep->bmAttributes != desc->bmAttributes
  476. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  477. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  478. DEBUG("%s: %s type mismatch\n", __func__, _ep->name);
  479. return -EINVAL;
  480. }
  481. /* hardware _could_ do smaller, but driver doesn't */
  482. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
  483. && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(ep))
  484. || !desc->wMaxPacketSize) {
  485. DEBUG("%s: bad %s maxpacket\n", __func__, _ep->name);
  486. return -ERANGE;
  487. }
  488. dev = ep->dev;
  489. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  490. DEBUG("%s: bogus device state\n", __func__);
  491. return -ESHUTDOWN;
  492. }
  493. ep->stopped = 0;
  494. ep->desc = desc;
  495. ep->pio_irqs = 0;
  496. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  497. /* Reset halt state */
  498. s3c_udc_set_nak(ep);
  499. s3c_udc_set_halt(_ep, 0);
  500. spin_lock_irqsave(&ep->dev->lock, flags);
  501. s3c_udc_ep_activate(ep);
  502. spin_unlock_irqrestore(&ep->dev->lock, flags);
  503. DEBUG("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  504. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  505. return 0;
  506. }
  507. /*
  508. * Disable EP
  509. */
  510. static int s3c_ep_disable(struct usb_ep *_ep)
  511. {
  512. struct s3c_ep *ep;
  513. unsigned long flags;
  514. DEBUG("%s: %p\n", __func__, _ep);
  515. ep = container_of(_ep, struct s3c_ep, ep);
  516. if (!_ep || !ep->desc) {
  517. DEBUG("%s: %s not enabled\n", __func__,
  518. _ep ? ep->ep.name : NULL);
  519. return -EINVAL;
  520. }
  521. spin_lock_irqsave(&ep->dev->lock, flags);
  522. /* Nuke all pending requests */
  523. nuke(ep, -ESHUTDOWN);
  524. ep->desc = 0;
  525. ep->stopped = 1;
  526. spin_unlock_irqrestore(&ep->dev->lock, flags);
  527. DEBUG("%s: disabled %s\n", __func__, _ep->name);
  528. return 0;
  529. }
  530. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  531. gfp_t gfp_flags)
  532. {
  533. struct s3c_request *req;
  534. DEBUG("%s: %s %p\n", __func__, ep->name, ep);
  535. req = kmalloc(sizeof *req, gfp_flags);
  536. if (!req)
  537. return 0;
  538. memset(req, 0, sizeof *req);
  539. INIT_LIST_HEAD(&req->queue);
  540. return &req->req;
  541. }
  542. static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
  543. {
  544. struct s3c_request *req;
  545. DEBUG("%s: %p\n", __func__, ep);
  546. req = container_of(_req, struct s3c_request, req);
  547. WARN_ON(!list_empty(&req->queue));
  548. kfree(req);
  549. }
  550. /* dequeue JUST ONE request */
  551. static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  552. {
  553. struct s3c_ep *ep;
  554. struct s3c_request *req;
  555. unsigned long flags;
  556. DEBUG("%s: %p\n", __func__, _ep);
  557. ep = container_of(_ep, struct s3c_ep, ep);
  558. if (!_ep || ep->ep.name == ep0name)
  559. return -EINVAL;
  560. spin_lock_irqsave(&ep->dev->lock, flags);
  561. /* make sure it's actually queued on this endpoint */
  562. list_for_each_entry(req, &ep->queue, queue) {
  563. if (&req->req == _req)
  564. break;
  565. }
  566. if (&req->req != _req) {
  567. spin_unlock_irqrestore(&ep->dev->lock, flags);
  568. return -EINVAL;
  569. }
  570. done(ep, req, -ECONNRESET);
  571. spin_unlock_irqrestore(&ep->dev->lock, flags);
  572. return 0;
  573. }
  574. /*
  575. * Return bytes in EP FIFO
  576. */
  577. static int s3c_fifo_status(struct usb_ep *_ep)
  578. {
  579. int count = 0;
  580. struct s3c_ep *ep;
  581. ep = container_of(_ep, struct s3c_ep, ep);
  582. if (!_ep) {
  583. DEBUG("%s: bad ep\n", __func__);
  584. return -ENODEV;
  585. }
  586. DEBUG("%s: %d\n", __func__, ep_index(ep));
  587. /* LPD can't report unclaimed bytes from IN fifos */
  588. if (ep_is_in(ep))
  589. return -EOPNOTSUPP;
  590. return count;
  591. }
  592. /*
  593. * Flush EP FIFO
  594. */
  595. static void s3c_fifo_flush(struct usb_ep *_ep)
  596. {
  597. struct s3c_ep *ep;
  598. ep = container_of(_ep, struct s3c_ep, ep);
  599. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  600. DEBUG("%s: bad ep\n", __func__);
  601. return;
  602. }
  603. DEBUG("%s: %d\n", __func__, ep_index(ep));
  604. }
  605. static const struct usb_gadget_ops s3c_udc_ops = {
  606. /* current versions must always be self-powered */
  607. };
  608. static struct s3c_udc memory = {
  609. .usb_address = 0,
  610. .gadget = {
  611. .ops = &s3c_udc_ops,
  612. .ep0 = &memory.ep[0].ep,
  613. .name = driver_name,
  614. },
  615. /* control endpoint */
  616. .ep[0] = {
  617. .ep = {
  618. .name = ep0name,
  619. .ops = &s3c_ep_ops,
  620. .maxpacket = EP0_FIFO_SIZE,
  621. },
  622. .dev = &memory,
  623. .bEndpointAddress = 0,
  624. .bmAttributes = 0,
  625. .ep_type = ep_control,
  626. },
  627. /* first group of endpoints */
  628. .ep[1] = {
  629. .ep = {
  630. .name = "ep1in-bulk",
  631. .ops = &s3c_ep_ops,
  632. .maxpacket = EP_FIFO_SIZE,
  633. },
  634. .dev = &memory,
  635. .bEndpointAddress = USB_DIR_IN | 1,
  636. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  637. .ep_type = ep_bulk_out,
  638. .fifo_num = 1,
  639. },
  640. .ep[2] = {
  641. .ep = {
  642. .name = "ep2out-bulk",
  643. .ops = &s3c_ep_ops,
  644. .maxpacket = EP_FIFO_SIZE,
  645. },
  646. .dev = &memory,
  647. .bEndpointAddress = USB_DIR_OUT | 2,
  648. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  649. .ep_type = ep_bulk_in,
  650. .fifo_num = 2,
  651. },
  652. .ep[3] = {
  653. .ep = {
  654. .name = "ep3in-int",
  655. .ops = &s3c_ep_ops,
  656. .maxpacket = EP_FIFO_SIZE,
  657. },
  658. .dev = &memory,
  659. .bEndpointAddress = USB_DIR_IN | 3,
  660. .bmAttributes = USB_ENDPOINT_XFER_INT,
  661. .ep_type = ep_interrupt,
  662. .fifo_num = 3,
  663. },
  664. };
  665. /*
  666. * probe - binds to the platform device
  667. */
  668. int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
  669. {
  670. struct s3c_udc *dev = &memory;
  671. int retval = 0, i;
  672. DEBUG("%s: %p\n", __func__, pdata);
  673. dev->pdata = pdata;
  674. phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
  675. reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
  676. usb_phy_ctrl = pdata->usb_phy_ctrl;
  677. /* regs_otg = (void *)pdata->regs_otg; */
  678. dev->gadget.is_dualspeed = 1; /* Hack only*/
  679. dev->gadget.is_otg = 0;
  680. dev->gadget.is_a_peripheral = 0;
  681. dev->gadget.b_hnp_enable = 0;
  682. dev->gadget.a_hnp_support = 0;
  683. dev->gadget.a_alt_hnp_support = 0;
  684. the_controller = dev;
  685. for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
  686. dev->dma_buf[i] = kmalloc(DMA_BUFFER_SIZE, GFP_KERNEL);
  687. dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
  688. invalidate_dcache_range((unsigned long) dev->dma_buf[i],
  689. (unsigned long) (dev->dma_buf[i]
  690. + DMA_BUFFER_SIZE));
  691. }
  692. usb_ctrl = dev->dma_buf[0];
  693. usb_ctrl_dma_addr = dev->dma_addr[0];
  694. udc_reinit(dev);
  695. return retval;
  696. }
  697. int usb_gadget_handle_interrupts()
  698. {
  699. u32 intr_status = readl(&reg->gintsts);
  700. u32 gintmsk = readl(&reg->gintmsk);
  701. if (intr_status & gintmsk)
  702. return s3c_udc_irq(1, (void *)the_controller);
  703. return 0;
  704. }