immap_85xx.h 68 KB

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  1. /*
  2. * MPC85xx Internal Memory Map
  3. *
  4. * Copyright 2007-2009 Freescale Semiconductor, Inc.
  5. *
  6. * Copyright(c) 2002,2003 Motorola Inc.
  7. * Xianghua Xiao (x.xiao@motorola.com)
  8. *
  9. */
  10. #ifndef __IMMAP_85xx__
  11. #define __IMMAP_85xx__
  12. #include <asm/types.h>
  13. #include <asm/fsl_dma.h>
  14. #include <asm/fsl_i2c.h>
  15. #include <asm/fsl_lbc.h>
  16. /*
  17. * Local-Access Registers and ECM Registers(0x0000-0x2000)
  18. */
  19. typedef struct ccsr_local_ecm {
  20. uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
  21. char res1[4];
  22. uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
  23. char res2[4];
  24. uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
  25. char res3[12];
  26. uint bptr; /* 0x20 - Boot Page Translation Register */
  27. char res4[3044];
  28. uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
  29. char res5[4];
  30. uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
  31. char res6[20];
  32. uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
  33. char res7[4];
  34. uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
  35. char res8[20];
  36. uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
  37. char res9[4];
  38. uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
  39. char res10[20];
  40. uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
  41. char res11[4];
  42. uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
  43. char res12[20];
  44. uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
  45. char res13[4];
  46. uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
  47. char res14[20];
  48. uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
  49. char res15[4];
  50. uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
  51. char res16[20];
  52. uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
  53. char res17[4];
  54. uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
  55. char res18[20];
  56. uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
  57. char res19[4];
  58. uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
  59. char res19_8a[20];
  60. uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
  61. char res19_8b[4];
  62. uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
  63. char res19_9a[20];
  64. uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
  65. char res19_9b[4];
  66. uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
  67. char res19_10a[20];
  68. uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */
  69. char res19_10b[4];
  70. uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */
  71. char res19_11a[20];
  72. uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */
  73. char res19_11b[4];
  74. uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */
  75. char res20[652];
  76. uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
  77. char res21[12];
  78. uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
  79. char res22[3564];
  80. uint eedr; /* 0x1e00 - ECM Error Detect Register */
  81. char res23[4];
  82. uint eeer; /* 0x1e08 - ECM Error Enable Register */
  83. uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
  84. uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
  85. char res24[492];
  86. } ccsr_local_ecm_t;
  87. /*
  88. * DDR memory controller registers(0x2000-0x3000)
  89. */
  90. typedef struct ccsr_ddr {
  91. uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
  92. char res1[4];
  93. uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
  94. char res2[4];
  95. uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
  96. char res3[4];
  97. uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
  98. char res4[100];
  99. uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
  100. uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
  101. uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
  102. uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
  103. char res4a[48];
  104. uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */
  105. uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */
  106. uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
  107. uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
  108. char res5[48];
  109. uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
  110. uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
  111. uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
  112. uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
  113. uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
  114. uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
  115. uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
  116. uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
  117. uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
  118. uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
  119. uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
  120. char res6[4];
  121. uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
  122. char res7[20];
  123. uint init_addr; /* 0x2148 - DDR training initialization address */
  124. uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
  125. char res8_1[16];
  126. uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
  127. uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
  128. char reg8_1a[8];
  129. uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
  130. uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
  131. uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/
  132. uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
  133. uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
  134. uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
  135. char res8_1b[2456];
  136. uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */
  137. uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */
  138. uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */
  139. uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */
  140. char res8_1c[200];
  141. uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
  142. uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
  143. char res8_2[512];
  144. uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
  145. uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
  146. uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
  147. char res9[20];
  148. uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
  149. uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
  150. uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
  151. char res10[20];
  152. uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
  153. uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
  154. uint err_int_en; /* 0x2e48 - DDR */
  155. uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
  156. uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
  157. uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
  158. uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
  159. char res11[164];
  160. uint debug_1; /* 0x2f00 */
  161. uint debug_2;
  162. uint debug_3;
  163. uint debug_4;
  164. char res12[240];
  165. } ccsr_ddr_t;
  166. /*
  167. * I2C Registers(0x3000-0x4000)
  168. */
  169. typedef struct ccsr_i2c {
  170. struct fsl_i2c i2c[1];
  171. u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
  172. } ccsr_i2c_t;
  173. #if defined(CONFIG_MPC8540) \
  174. || defined(CONFIG_MPC8541) \
  175. || defined(CONFIG_MPC8548) \
  176. || defined(CONFIG_MPC8555)
  177. /* DUART Registers(0x4000-0x5000) */
  178. typedef struct ccsr_duart {
  179. char res1[1280];
  180. u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
  181. u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
  182. u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
  183. u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
  184. u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
  185. u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
  186. u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
  187. u_char uscr1; /* 0x4507 - UART1 Scratch Register */
  188. char res2[8];
  189. u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
  190. char res3[239];
  191. u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
  192. u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
  193. u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
  194. u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
  195. u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
  196. u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
  197. u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
  198. u_char uscr2; /* 0x4607 - UART2 Scratch Register */
  199. char res4[8];
  200. u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
  201. char res5[2543];
  202. } ccsr_duart_t;
  203. #else /* MPC8560 uses UART on its CPM */
  204. typedef struct ccsr_duart {
  205. char res[4096];
  206. } ccsr_duart_t;
  207. #endif
  208. /* Local Bus Controller Registers(0x5000-0x6000) */
  209. /* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
  210. typedef struct ccsr_lbc {
  211. uint br0; /* 0x5000 - LBC Base Register 0 */
  212. uint or0; /* 0x5004 - LBC Options Register 0 */
  213. uint br1; /* 0x5008 - LBC Base Register 1 */
  214. uint or1; /* 0x500c - LBC Options Register 1 */
  215. uint br2; /* 0x5010 - LBC Base Register 2 */
  216. uint or2; /* 0x5014 - LBC Options Register 2 */
  217. uint br3; /* 0x5018 - LBC Base Register 3 */
  218. uint or3; /* 0x501c - LBC Options Register 3 */
  219. uint br4; /* 0x5020 - LBC Base Register 4 */
  220. uint or4; /* 0x5024 - LBC Options Register 4 */
  221. uint br5; /* 0x5028 - LBC Base Register 5 */
  222. uint or5; /* 0x502c - LBC Options Register 5 */
  223. uint br6; /* 0x5030 - LBC Base Register 6 */
  224. uint or6; /* 0x5034 - LBC Options Register 6 */
  225. uint br7; /* 0x5038 - LBC Base Register 7 */
  226. uint or7; /* 0x503c - LBC Options Register 7 */
  227. char res1[40];
  228. uint mar; /* 0x5068 - LBC UPM Address Register */
  229. char res2[4];
  230. uint mamr; /* 0x5070 - LBC UPMA Mode Register */
  231. uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
  232. uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
  233. char res3[8];
  234. uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
  235. uint mdr; /* 0x5088 - LBC UPM Data Register */
  236. char res4[8];
  237. uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
  238. char res5[8];
  239. uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
  240. uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
  241. char res6[8];
  242. uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
  243. uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
  244. uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
  245. uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
  246. uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
  247. char res7[12];
  248. uint lbcr; /* 0x50d0 - LBC Configuration Register */
  249. uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
  250. char res8[3880];
  251. } ccsr_lbc_t;
  252. /*
  253. * eSPI Registers(0x7000-0x8000)
  254. */
  255. typedef struct ccsr_espi {
  256. uint mode; /* 0x00 - eSPI mode register */
  257. uint event; /* 0x04 - eSPI event register */
  258. uint mask; /* 0x08 - eSPI mask register */
  259. uint com; /* 0x0c - eSPI command register */
  260. uint tx; /* 0x10 - eSPI transmit FIFO access register */
  261. uint rx; /* 0x14 - eSPI receive FIFO access register */
  262. char res1[8]; /* reserved */
  263. uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */
  264. char res2[4048]; /* fill up to 0x1000 */
  265. } ccsr_espi_t;
  266. /*
  267. * PCI Registers(0x8000-0x9000)
  268. */
  269. typedef struct ccsr_pcix {
  270. uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
  271. uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
  272. uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
  273. char res1[3060];
  274. uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
  275. uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
  276. uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
  277. uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
  278. uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
  279. char res2[12];
  280. uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
  281. uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
  282. uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
  283. uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
  284. uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
  285. char res3[12];
  286. uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
  287. uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
  288. uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
  289. uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
  290. uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
  291. char res4[12];
  292. uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
  293. uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
  294. uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
  295. uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
  296. uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
  297. char res5[12];
  298. uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
  299. uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
  300. uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
  301. uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
  302. uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
  303. char res6[268];
  304. uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
  305. uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
  306. uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
  307. uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
  308. uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
  309. char res7[12];
  310. uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
  311. uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
  312. uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
  313. uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
  314. uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
  315. char res8[12];
  316. uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
  317. uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
  318. uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
  319. char res9[4];
  320. uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
  321. char res10[12];
  322. uint pedr; /* 0x8e00 - PCIX Error Detect Register */
  323. uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
  324. uint peer; /* 0x8e08 - PCIX Error Enable Register */
  325. uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
  326. uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
  327. uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
  328. uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
  329. uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
  330. uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
  331. char res11[476];
  332. } ccsr_pcix_t;
  333. #define PCIX_COMMAND 0x62
  334. #define POWAR_EN 0x80000000
  335. #define POWAR_IO_READ 0x00080000
  336. #define POWAR_MEM_READ 0x00040000
  337. #define POWAR_IO_WRITE 0x00008000
  338. #define POWAR_MEM_WRITE 0x00004000
  339. #define POWAR_MEM_512M 0x0000001c
  340. #define POWAR_IO_1M 0x00000013
  341. #define PIWAR_EN 0x80000000
  342. #define PIWAR_PF 0x20000000
  343. #define PIWAR_LOCAL 0x00f00000
  344. #define PIWAR_READ_SNOOP 0x00050000
  345. #define PIWAR_WRITE_SNOOP 0x00005000
  346. #define PIWAR_MEM_2G 0x0000001e
  347. /*
  348. * L2 Cache Registers(0x2_0000-0x2_1000)
  349. */
  350. typedef struct ccsr_l2cache {
  351. uint l2ctl; /* 0x20000 - L2 configuration register 0 */
  352. char res1[12];
  353. uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
  354. char res2[4];
  355. uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
  356. char res3[4];
  357. uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
  358. char res4[4];
  359. uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
  360. char res5[4];
  361. uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
  362. char res6[4];
  363. uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
  364. char res7[4];
  365. uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
  366. char res8[4];
  367. uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
  368. char res9[180];
  369. uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
  370. char res10[4];
  371. uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
  372. char res11[3316];
  373. uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
  374. uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
  375. uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
  376. char res12[20];
  377. uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
  378. uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
  379. uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
  380. char res13[20];
  381. uint l2errdet; /* 0x20e40 - L2 error detect register */
  382. uint l2errdis; /* 0x20e44 - L2 error disable register */
  383. uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
  384. uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
  385. uint l2erraddr; /* 0x20e50 - L2 error address capture register */
  386. char res14[4];
  387. uint l2errctl; /* 0x20e58 - L2 error control register */
  388. char res15[420];
  389. } ccsr_l2cache_t;
  390. /*
  391. * DMA Registers(0x2_1000-0x2_2000)
  392. */
  393. typedef struct ccsr_dma {
  394. char res1[256];
  395. struct fsl_dma dma[4];
  396. uint dgsr; /* 0x21300 - DMA General Status Register */
  397. char res2[11516];
  398. } ccsr_dma_t;
  399. /*
  400. * tsec1 tsec2: 24000-26000
  401. */
  402. typedef struct ccsr_tsec {
  403. char res1[16];
  404. uint ievent; /* 0x24010 - Interrupt Event Register */
  405. uint imask; /* 0x24014 - Interrupt Mask Register */
  406. uint edis; /* 0x24018 - Error Disabled Register */
  407. char res2[4];
  408. uint ecntrl; /* 0x24020 - Ethernet Control Register */
  409. uint minflr; /* 0x24024 - Minimum Frame Length Register */
  410. uint ptv; /* 0x24028 - Pause Time Value Register */
  411. uint dmactrl; /* 0x2402c - DMA Control Register */
  412. uint tbipa; /* 0x24030 - TBI PHY Address Register */
  413. char res3[88];
  414. uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
  415. char res4[8];
  416. uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
  417. uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
  418. char res5[96];
  419. uint tctrl; /* 0x24100 - Transmit Control Register */
  420. uint tstat; /* 0x24104 - Transmit Status Register */
  421. char res6[4];
  422. uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
  423. char res7[16];
  424. uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
  425. uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
  426. char res8[88];
  427. uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
  428. uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
  429. char res9[120];
  430. uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
  431. uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
  432. char res10[168];
  433. uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
  434. uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
  435. uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
  436. uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
  437. uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
  438. uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
  439. uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
  440. char res11[52];
  441. uint rctrl; /* 0x24300 - Receive Control Register */
  442. uint rstat; /* 0x24304 - Receive Status Register */
  443. char res12[4];
  444. uint rbdlen; /* 0x2430c - RxBD Data Length Register */
  445. char res13[16];
  446. uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
  447. uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
  448. char res14[24];
  449. uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
  450. uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
  451. char res15[56];
  452. uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
  453. uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
  454. uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
  455. uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
  456. uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
  457. uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
  458. uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
  459. uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
  460. char res16[96];
  461. uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
  462. uint rbase; /* 0x24404 - Receive Descriptor Base Address */
  463. uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
  464. uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
  465. uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
  466. uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
  467. uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
  468. uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
  469. char res17[224];
  470. uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
  471. uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
  472. uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
  473. uint hafdup; /* 0x2450c - Half Duplex Register */
  474. uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
  475. char res18[12];
  476. uint miimcfg; /* 0x24520 - MII Management Configuration Register */
  477. uint miimcom; /* 0x24524 - MII Management Command Register */
  478. uint miimadd; /* 0x24528 - MII Management Address Register */
  479. uint miimcon; /* 0x2452c - MII Management Control Register */
  480. uint miimstat; /* 0x24530 - MII Management Status Register */
  481. uint miimind; /* 0x24534 - MII Management Indicator Register */
  482. char res19[4];
  483. uint ifstat; /* 0x2453c - Interface Status Register */
  484. uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
  485. uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
  486. char res20[312];
  487. uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
  488. uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
  489. uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
  490. uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
  491. uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
  492. uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
  493. uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
  494. uint rbyt; /* 0x2469c - Receive Byte Counter */
  495. uint rpkt; /* 0x246a0 - Receive Packet Counter */
  496. uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
  497. uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
  498. uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
  499. uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
  500. uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
  501. uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
  502. uint raln; /* 0x246bc - Receive Alignment Error Counter */
  503. uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
  504. uint rcde; /* 0x246c4 - Receive Code Error Counter */
  505. uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
  506. uint rund; /* 0x246cc - Receive Undersize Packet Counter */
  507. uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
  508. uint rfrg; /* 0x246d4 - Receive Fragments Counter */
  509. uint rjbr; /* 0x246d8 - Receive Jabber Counter */
  510. uint rdrp; /* 0x246dc - Receive Drop Counter */
  511. uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
  512. uint tpkt; /* 0x246e4 - Transmit Packet Counter */
  513. uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
  514. uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
  515. uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
  516. uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
  517. uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
  518. uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
  519. uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
  520. uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
  521. uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
  522. uint tncl; /* 0x2470c - Transmit Total Collision Counter */
  523. char res21[4];
  524. uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
  525. uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
  526. uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
  527. uint txcf; /* 0x24720 - Transmit Control Frame Counter */
  528. uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
  529. uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
  530. uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
  531. uint car1; /* 0x24730 - Carry Register One */
  532. uint car2; /* 0x24734 - Carry Register Two */
  533. uint cam1; /* 0x24738 - Carry Mask Register One */
  534. uint cam2; /* 0x2473c - Carry Mask Register Two */
  535. char res22[192];
  536. uint iaddr0; /* 0x24800 - Indivdual address register 0 */
  537. uint iaddr1; /* 0x24804 - Indivdual address register 1 */
  538. uint iaddr2; /* 0x24808 - Indivdual address register 2 */
  539. uint iaddr3; /* 0x2480c - Indivdual address register 3 */
  540. uint iaddr4; /* 0x24810 - Indivdual address register 4 */
  541. uint iaddr5; /* 0x24814 - Indivdual address register 5 */
  542. uint iaddr6; /* 0x24818 - Indivdual address register 6 */
  543. uint iaddr7; /* 0x2481c - Indivdual address register 7 */
  544. char res23[96];
  545. uint gaddr0; /* 0x24880 - Global address register 0 */
  546. uint gaddr1; /* 0x24884 - Global address register 1 */
  547. uint gaddr2; /* 0x24888 - Global address register 2 */
  548. uint gaddr3; /* 0x2488c - Global address register 3 */
  549. uint gaddr4; /* 0x24890 - Global address register 4 */
  550. uint gaddr5; /* 0x24894 - Global address register 5 */
  551. uint gaddr6; /* 0x24898 - Global address register 6 */
  552. uint gaddr7; /* 0x2489c - Global address register 7 */
  553. char res24[96];
  554. uint pmd0; /* 0x24900 - Pattern Match Data Register */
  555. char res25[4];
  556. uint pmask0; /* 0x24908 - Pattern Mask Register */
  557. char res26[4];
  558. uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
  559. char res27[4];
  560. uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
  561. uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
  562. uint pmd1; /* 0x24920 - Pattern Match Data Register */
  563. char res28[4];
  564. uint pmask1; /* 0x24928 - Pattern Mask Register */
  565. char res29[4];
  566. uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
  567. char res30[4];
  568. uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
  569. uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
  570. uint pmd2; /* 0x24940 - Pattern Match Data Register */
  571. char res31[4];
  572. uint pmask2; /* 0x24948 - Pattern Mask Register */
  573. char res32[4];
  574. uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
  575. char res33[4];
  576. uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
  577. uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
  578. uint pmd3; /* 0x24960 - Pattern Match Data Register */
  579. char res34[4];
  580. uint pmask3; /* 0x24968 - Pattern Mask Register */
  581. char res35[4];
  582. uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
  583. char res36[4];
  584. uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
  585. uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
  586. uint pmd4; /* 0x24980 - Pattern Match Data Register */
  587. char res37[4];
  588. uint pmask4; /* 0x24988 - Pattern Mask Register */
  589. char res38[4];
  590. uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
  591. char res39[4];
  592. uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
  593. uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
  594. uint pmd5; /* 0x249a0 - Pattern Match Data Register */
  595. char res40[4];
  596. uint pmask5; /* 0x249a8 - Pattern Mask Register */
  597. char res41[4];
  598. uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
  599. char res42[4];
  600. uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
  601. uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
  602. uint pmd6; /* 0x249c0 - Pattern Match Data Register */
  603. char res43[4];
  604. uint pmask6; /* 0x249c8 - Pattern Mask Register */
  605. char res44[4];
  606. uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
  607. char res45[4];
  608. uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
  609. uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
  610. uint pmd7; /* 0x249e0 - Pattern Match Data Register */
  611. char res46[4];
  612. uint pmask7; /* 0x249e8 - Pattern Mask Register */
  613. char res47[4];
  614. uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
  615. char res48[4];
  616. uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
  617. uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
  618. uint pmd8; /* 0x24a00 - Pattern Match Data Register */
  619. char res49[4];
  620. uint pmask8; /* 0x24a08 - Pattern Mask Register */
  621. char res50[4];
  622. uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
  623. char res51[4];
  624. uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
  625. uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
  626. uint pmd9; /* 0x24a20 - Pattern Match Data Register */
  627. char res52[4];
  628. uint pmask9; /* 0x24a28 - Pattern Mask Register */
  629. char res53[4];
  630. uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
  631. char res54[4];
  632. uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
  633. uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
  634. uint pmd10; /* 0x24a40 - Pattern Match Data Register */
  635. char res55[4];
  636. uint pmask10; /* 0x24a48 - Pattern Mask Register */
  637. char res56[4];
  638. uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
  639. char res57[4];
  640. uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
  641. uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
  642. uint pmd11; /* 0x24a60 - Pattern Match Data Register */
  643. char res58[4];
  644. uint pmask11; /* 0x24a68 - Pattern Mask Register */
  645. char res59[4];
  646. uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
  647. char res60[4];
  648. uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
  649. uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
  650. uint pmd12; /* 0x24a80 - Pattern Match Data Register */
  651. char res61[4];
  652. uint pmask12; /* 0x24a88 - Pattern Mask Register */
  653. char res62[4];
  654. uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
  655. char res63[4];
  656. uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
  657. uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
  658. uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
  659. char res64[4];
  660. uint pmask13; /* 0x24aa8 - Pattern Mask Register */
  661. char res65[4];
  662. uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
  663. char res66[4];
  664. uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
  665. uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
  666. uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
  667. char res67[4];
  668. uint pmask14; /* 0x24ac8 - Pattern Mask Register */
  669. char res68[4];
  670. uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
  671. char res69[4];
  672. uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
  673. uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
  674. uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
  675. char res70[4];
  676. uint pmask15; /* 0x24ae8 - Pattern Mask Register */
  677. char res71[4];
  678. uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
  679. char res72[4];
  680. uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
  681. uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
  682. char res73[248];
  683. uint attr; /* 0x24bf8 - Attributes Register */
  684. uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
  685. char res74[1024];
  686. } ccsr_tsec_t;
  687. /*
  688. * PIC Registers(0x4_0000-0x8_0000)
  689. */
  690. typedef struct ccsr_pic {
  691. char res1[64]; /* 0x40000 */
  692. uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
  693. char res2[12];
  694. uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
  695. char res3[12];
  696. uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
  697. char res4[12];
  698. uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
  699. char res5[12];
  700. uint ctpr; /* 0x40080 - Current Task Priority Register */
  701. char res6[12];
  702. uint whoami; /* 0x40090 - Who Am I Register */
  703. char res7[12];
  704. uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
  705. char res8[12];
  706. uint eoi; /* 0x400b0 - End Of Interrupt Register */
  707. char res9[3916];
  708. uint frr; /* 0x41000 - Feature Reporting Register */
  709. char res10[28];
  710. uint gcr; /* 0x41020 - Global Configuration Register */
  711. #define MPC85xx_PICGCR_RST 0x80000000
  712. #define MPC85xx_PICGCR_M 0x20000000
  713. char res11[92];
  714. uint vir; /* 0x41080 - Vendor Identification Register */
  715. char res12[12];
  716. uint pir; /* 0x41090 - Processor Initialization Register */
  717. char res13[12];
  718. uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
  719. char res14[12];
  720. uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
  721. char res15[12];
  722. uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
  723. char res16[12];
  724. uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
  725. char res17[12];
  726. uint svr; /* 0x410e0 - Spurious Vector Register */
  727. char res18[12];
  728. uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
  729. char res19[12];
  730. uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
  731. char res20[12];
  732. uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
  733. char res21[12];
  734. uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
  735. char res22[12];
  736. uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
  737. char res23[12];
  738. uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
  739. char res24[12];
  740. uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
  741. char res25[12];
  742. uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
  743. char res26[12];
  744. uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
  745. char res27[12];
  746. uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
  747. char res28[12];
  748. uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
  749. char res29[12];
  750. uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
  751. char res30[12];
  752. uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
  753. char res31[12];
  754. uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
  755. char res32[12];
  756. uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
  757. char res33[12];
  758. uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
  759. char res34[12];
  760. uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
  761. char res35[268];
  762. uint tcr; /* 0x41300 - Timer Control Register */
  763. char res36[12];
  764. uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
  765. char res37[12];
  766. uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
  767. char res38[12];
  768. uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
  769. char res39[12];
  770. uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
  771. char res40[188];
  772. uint msgr0; /* 0x41400 - Message Register 0 */
  773. char res41[12];
  774. uint msgr1; /* 0x41410 - Message Register 1 */
  775. char res42[12];
  776. uint msgr2; /* 0x41420 - Message Register 2 */
  777. char res43[12];
  778. uint msgr3; /* 0x41430 - Message Register 3 */
  779. char res44[204];
  780. uint mer; /* 0x41500 - Message Enable Register */
  781. char res45[12];
  782. uint msr; /* 0x41510 - Message Status Register */
  783. char res46[60140];
  784. uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
  785. char res47[12];
  786. uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
  787. char res48[12];
  788. uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
  789. char res49[12];
  790. uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
  791. char res50[12];
  792. uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
  793. char res51[12];
  794. uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
  795. char res52[12];
  796. uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
  797. char res53[12];
  798. uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
  799. char res54[12];
  800. uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
  801. char res55[12];
  802. uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
  803. char res56[12];
  804. uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
  805. char res57[12];
  806. uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
  807. char res58[12];
  808. uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
  809. char res59[12];
  810. uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
  811. char res60[12];
  812. uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
  813. char res61[12];
  814. uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
  815. char res62[12];
  816. uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
  817. char res63[12];
  818. uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
  819. char res64[12];
  820. uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
  821. char res65[12];
  822. uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
  823. char res66[12];
  824. uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
  825. char res67[12];
  826. uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
  827. char res68[12];
  828. uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
  829. char res69[12];
  830. uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
  831. char res70[140];
  832. uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
  833. char res71[12];
  834. uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
  835. char res72[12];
  836. uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
  837. char res73[12];
  838. uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
  839. char res74[12];
  840. uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
  841. char res75[12];
  842. uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
  843. char res76[12];
  844. uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
  845. char res77[12];
  846. uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
  847. char res78[12];
  848. uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
  849. char res79[12];
  850. uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
  851. char res80[12];
  852. uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
  853. char res81[12];
  854. uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
  855. char res82[12];
  856. uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
  857. char res83[12];
  858. uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
  859. char res84[12];
  860. uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
  861. char res85[12];
  862. uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
  863. char res86[12];
  864. uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
  865. char res87[12];
  866. uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
  867. char res88[12];
  868. uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
  869. char res89[12];
  870. uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
  871. char res90[12];
  872. uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
  873. char res91[12];
  874. uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
  875. char res92[12];
  876. uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
  877. char res93[12];
  878. uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
  879. char res94[12];
  880. uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
  881. char res95[12];
  882. uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
  883. char res96[12];
  884. uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
  885. char res97[12];
  886. uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
  887. char res98[12];
  888. uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
  889. char res99[12];
  890. uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
  891. char res100[12];
  892. uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
  893. char res101[12];
  894. uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
  895. char res102[12];
  896. uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
  897. char res103[12];
  898. uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
  899. char res104[12];
  900. uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
  901. char res105[12];
  902. uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
  903. char res106[12];
  904. uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
  905. char res107[12];
  906. uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
  907. char res108[12];
  908. uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
  909. char res109[12];
  910. uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
  911. char res110[12];
  912. uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
  913. char res111[12];
  914. uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
  915. char res112[12];
  916. uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
  917. char res113[12];
  918. uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
  919. char res114[12];
  920. uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
  921. char res115[12];
  922. uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
  923. char res116[12];
  924. uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
  925. char res117[12];
  926. uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
  927. char res118[12];
  928. uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
  929. char res119[12];
  930. uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
  931. char res120[12];
  932. uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
  933. char res121[12];
  934. uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
  935. char res122[12];
  936. uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
  937. char res123[12];
  938. uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
  939. char res124[12];
  940. uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
  941. char res125[12];
  942. uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
  943. char res126[12];
  944. uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
  945. char res127[12];
  946. uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
  947. char res128[12];
  948. uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
  949. char res129[12];
  950. uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
  951. char res130[12];
  952. uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
  953. char res131[12];
  954. uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
  955. char res132[12];
  956. uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
  957. char res133[12];
  958. uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
  959. char res134[4108];
  960. uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
  961. char res135[12];
  962. uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
  963. char res136[12];
  964. uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
  965. char res137[12];
  966. uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
  967. char res138[12];
  968. uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
  969. char res139[12];
  970. uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
  971. char res140[12];
  972. uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
  973. char res141[12];
  974. uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
  975. char res142[59852];
  976. uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
  977. char res143[12];
  978. uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
  979. char res144[12];
  980. uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
  981. char res145[12];
  982. uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
  983. char res146[12];
  984. uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
  985. char res147[12];
  986. uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
  987. char res148[12];
  988. uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
  989. char res149[12];
  990. uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
  991. char res150[130892];
  992. } ccsr_pic_t;
  993. /*
  994. * CPM Block(0x8_0000-0xc_0000)
  995. */
  996. #ifndef CONFIG_CPM2
  997. typedef struct ccsr_cpm {
  998. char res[262144];
  999. } ccsr_cpm_t;
  1000. #else
  1001. /*
  1002. * 0x8000-0x8ffff:DPARM
  1003. * 0x9000-0x90bff: General SIU
  1004. */
  1005. typedef struct ccsr_cpm_siu {
  1006. char res1[80];
  1007. uint smaer;
  1008. uint smser;
  1009. uint smevr;
  1010. char res2[4];
  1011. uint lmaer;
  1012. uint lmser;
  1013. uint lmevr;
  1014. char res3[2964];
  1015. } ccsr_cpm_siu_t;
  1016. /* 0x90c00-0x90cff: Interrupt Controller */
  1017. typedef struct ccsr_cpm_intctl {
  1018. ushort sicr;
  1019. char res1[2];
  1020. uint sivec;
  1021. uint sipnrh;
  1022. uint sipnrl;
  1023. uint siprr;
  1024. uint scprrh;
  1025. uint scprrl;
  1026. uint simrh;
  1027. uint simrl;
  1028. uint siexr;
  1029. char res2[88];
  1030. uint sccr;
  1031. char res3[124];
  1032. } ccsr_cpm_intctl_t;
  1033. /* 0x90d00-0x90d7f: input/output port */
  1034. typedef struct ccsr_cpm_iop {
  1035. uint pdira;
  1036. uint ppara;
  1037. uint psora;
  1038. uint podra;
  1039. uint pdata;
  1040. char res1[12];
  1041. uint pdirb;
  1042. uint pparb;
  1043. uint psorb;
  1044. uint podrb;
  1045. uint pdatb;
  1046. char res2[12];
  1047. uint pdirc;
  1048. uint pparc;
  1049. uint psorc;
  1050. uint podrc;
  1051. uint pdatc;
  1052. char res3[12];
  1053. uint pdird;
  1054. uint ppard;
  1055. uint psord;
  1056. uint podrd;
  1057. uint pdatd;
  1058. char res4[12];
  1059. } ccsr_cpm_iop_t;
  1060. /* 0x90d80-0x91017: CPM timers */
  1061. typedef struct ccsr_cpm_timer {
  1062. u_char tgcr1;
  1063. char res1[3];
  1064. u_char tgcr2;
  1065. char res2[11];
  1066. ushort tmr1;
  1067. ushort tmr2;
  1068. ushort trr1;
  1069. ushort trr2;
  1070. ushort tcr1;
  1071. ushort tcr2;
  1072. ushort tcn1;
  1073. ushort tcn2;
  1074. ushort tmr3;
  1075. ushort tmr4;
  1076. ushort trr3;
  1077. ushort trr4;
  1078. ushort tcr3;
  1079. ushort tcr4;
  1080. ushort tcn3;
  1081. ushort tcn4;
  1082. ushort ter1;
  1083. ushort ter2;
  1084. ushort ter3;
  1085. ushort ter4;
  1086. char res3[608];
  1087. } ccsr_cpm_timer_t;
  1088. /* 0x91018-0x912ff: SDMA */
  1089. typedef struct ccsr_cpm_sdma {
  1090. uchar sdsr;
  1091. char res1[3];
  1092. uchar sdmr;
  1093. char res2[739];
  1094. } ccsr_cpm_sdma_t;
  1095. /* 0x91300-0x9131f: FCC1 */
  1096. typedef struct ccsr_cpm_fcc1 {
  1097. uint gfmr;
  1098. uint fpsmr;
  1099. ushort ftodr;
  1100. char res1[2];
  1101. ushort fdsr;
  1102. char res2[2];
  1103. ushort fcce;
  1104. char res3[2];
  1105. ushort fccm;
  1106. char res4[2];
  1107. u_char fccs;
  1108. char res5[3];
  1109. u_char ftirr_phy[4];
  1110. } ccsr_cpm_fcc1_t;
  1111. /* 0x91320-0x9133f: FCC2 */
  1112. typedef struct ccsr_cpm_fcc2 {
  1113. uint gfmr;
  1114. uint fpsmr;
  1115. ushort ftodr;
  1116. char res1[2];
  1117. ushort fdsr;
  1118. char res2[2];
  1119. ushort fcce;
  1120. char res3[2];
  1121. ushort fccm;
  1122. char res4[2];
  1123. u_char fccs;
  1124. char res5[3];
  1125. u_char ftirr_phy[4];
  1126. } ccsr_cpm_fcc2_t;
  1127. /* 0x91340-0x9137f: FCC3 */
  1128. typedef struct ccsr_cpm_fcc3 {
  1129. uint gfmr;
  1130. uint fpsmr;
  1131. ushort ftodr;
  1132. char res1[2];
  1133. ushort fdsr;
  1134. char res2[2];
  1135. ushort fcce;
  1136. char res3[2];
  1137. ushort fccm;
  1138. char res4[2];
  1139. u_char fccs;
  1140. char res5[3];
  1141. char res[36];
  1142. } ccsr_cpm_fcc3_t;
  1143. /* 0x91380-0x9139f: FCC1 extended */
  1144. typedef struct ccsr_cpm_fcc1_ext {
  1145. uint firper;
  1146. uint firer;
  1147. uint firsr_h;
  1148. uint firsr_l;
  1149. u_char gfemr;
  1150. char res[15];
  1151. } ccsr_cpm_fcc1_ext_t;
  1152. /* 0x913a0-0x913cf: FCC2 extended */
  1153. typedef struct ccsr_cpm_fcc2_ext {
  1154. uint firper;
  1155. uint firer;
  1156. uint firsr_h;
  1157. uint firsr_l;
  1158. u_char gfemr;
  1159. char res[31];
  1160. } ccsr_cpm_fcc2_ext_t;
  1161. /* 0x913d0-0x913ff: FCC3 extended */
  1162. typedef struct ccsr_cpm_fcc3_ext {
  1163. u_char gfemr;
  1164. char res[47];
  1165. } ccsr_cpm_fcc3_ext_t;
  1166. /* 0x91400-0x915ef: TC layers */
  1167. typedef struct ccsr_cpm_tmp1 {
  1168. char res[496];
  1169. } ccsr_cpm_tmp1_t;
  1170. /* 0x915f0-0x9185f: BRGs:5,6,7,8 */
  1171. typedef struct ccsr_cpm_brg2 {
  1172. uint brgc5;
  1173. uint brgc6;
  1174. uint brgc7;
  1175. uint brgc8;
  1176. char res[608];
  1177. } ccsr_cpm_brg2_t;
  1178. /* 0x91860-0x919bf: I2C */
  1179. typedef struct ccsr_cpm_i2c {
  1180. u_char i2mod;
  1181. char res1[3];
  1182. u_char i2add;
  1183. char res2[3];
  1184. u_char i2brg;
  1185. char res3[3];
  1186. u_char i2com;
  1187. char res4[3];
  1188. u_char i2cer;
  1189. char res5[3];
  1190. u_char i2cmr;
  1191. char res6[331];
  1192. } ccsr_cpm_i2c_t;
  1193. /* 0x919c0-0x919ef: CPM core */
  1194. typedef struct ccsr_cpm_cp {
  1195. uint cpcr;
  1196. uint rccr;
  1197. char res1[14];
  1198. ushort rter;
  1199. char res2[2];
  1200. ushort rtmr;
  1201. ushort rtscr;
  1202. char res3[2];
  1203. uint rtsr;
  1204. char res4[12];
  1205. } ccsr_cpm_cp_t;
  1206. /* 0x919f0-0x919ff: BRGs:1,2,3,4 */
  1207. typedef struct ccsr_cpm_brg1 {
  1208. uint brgc1;
  1209. uint brgc2;
  1210. uint brgc3;
  1211. uint brgc4;
  1212. } ccsr_cpm_brg1_t;
  1213. /* 0x91a00-0x91a9f: SCC1-SCC4 */
  1214. typedef struct ccsr_cpm_scc {
  1215. uint gsmrl;
  1216. uint gsmrh;
  1217. ushort psmr;
  1218. char res1[2];
  1219. ushort todr;
  1220. ushort dsr;
  1221. ushort scce;
  1222. char res2[2];
  1223. ushort sccm;
  1224. char res3;
  1225. u_char sccs;
  1226. char res4[8];
  1227. } ccsr_cpm_scc_t;
  1228. /* 0x91a80-0x91a9f */
  1229. typedef struct ccsr_cpm_tmp2 {
  1230. char res[32];
  1231. } ccsr_cpm_tmp2_t;
  1232. /* 0x91aa0-0x91aff: SPI */
  1233. typedef struct ccsr_cpm_spi {
  1234. ushort spmode;
  1235. char res1[4];
  1236. u_char spie;
  1237. char res2[3];
  1238. u_char spim;
  1239. char res3[2];
  1240. u_char spcom;
  1241. char res4[82];
  1242. } ccsr_cpm_spi_t;
  1243. /* 0x91b00-0x91b1f: CPM MUX */
  1244. typedef struct ccsr_cpm_mux {
  1245. u_char cmxsi1cr;
  1246. char res1;
  1247. u_char cmxsi2cr;
  1248. char res2;
  1249. uint cmxfcr;
  1250. uint cmxscr;
  1251. char res3[2];
  1252. ushort cmxuar;
  1253. char res4[16];
  1254. } ccsr_cpm_mux_t;
  1255. /* 0x91b20-0xbffff: SI,MCC,etc */
  1256. typedef struct ccsr_cpm_tmp3 {
  1257. char res[58592];
  1258. } ccsr_cpm_tmp3_t;
  1259. typedef struct ccsr_cpm_iram {
  1260. unsigned long iram[8192];
  1261. char res[98304];
  1262. } ccsr_cpm_iram_t;
  1263. typedef struct ccsr_cpm {
  1264. /* Some references are into the unique and known dpram spaces,
  1265. * others are from the generic base.
  1266. */
  1267. #define im_dprambase im_dpram1
  1268. u_char im_dpram1[16*1024];
  1269. char res1[16*1024];
  1270. u_char im_dpram2[16*1024];
  1271. char res2[16*1024];
  1272. ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
  1273. ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
  1274. ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
  1275. ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
  1276. ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
  1277. ccsr_cpm_fcc1_t im_cpm_fcc1;
  1278. ccsr_cpm_fcc2_t im_cpm_fcc2;
  1279. ccsr_cpm_fcc3_t im_cpm_fcc3;
  1280. ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
  1281. ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
  1282. ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
  1283. ccsr_cpm_tmp1_t im_cpm_tmp1;
  1284. ccsr_cpm_brg2_t im_cpm_brg2;
  1285. ccsr_cpm_i2c_t im_cpm_i2c;
  1286. ccsr_cpm_cp_t im_cpm_cp;
  1287. ccsr_cpm_brg1_t im_cpm_brg1;
  1288. ccsr_cpm_scc_t im_cpm_scc[4];
  1289. ccsr_cpm_tmp2_t im_cpm_tmp2;
  1290. ccsr_cpm_spi_t im_cpm_spi;
  1291. ccsr_cpm_mux_t im_cpm_mux;
  1292. ccsr_cpm_tmp3_t im_cpm_tmp3;
  1293. ccsr_cpm_iram_t im_cpm_iram;
  1294. } ccsr_cpm_t;
  1295. #endif
  1296. /*
  1297. * RapidIO Registers(0xc_0000-0xe_0000)
  1298. */
  1299. typedef struct ccsr_rio {
  1300. uint didcar; /* 0xc0000 - Device Identity Capability Register */
  1301. uint dicar; /* 0xc0004 - Device Information Capability Register */
  1302. uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
  1303. uint aicar; /* 0xc000c - Assembly Information Capability Register */
  1304. uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
  1305. uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
  1306. uint socar; /* 0xc0018 - Source Operations Capability Register */
  1307. uint docar; /* 0xc001c - Destination Operations Capability Register */
  1308. char res1[32];
  1309. uint msr; /* 0xc0040 - Mailbox Command And Status Register */
  1310. uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
  1311. char res2[4];
  1312. uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
  1313. char res3[12];
  1314. uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
  1315. uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
  1316. char res4[4];
  1317. uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
  1318. uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
  1319. char res5[144];
  1320. uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
  1321. char res6[28];
  1322. uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
  1323. uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
  1324. char res7[20];
  1325. uint pgccsr; /* 0xc013c - Port General Command and Status Register */
  1326. uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
  1327. uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
  1328. uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
  1329. char res8[12];
  1330. uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
  1331. uint pccsr; /* 0xc015c - Port Control Command and Status Register */
  1332. char res9[65184];
  1333. uint cr; /* 0xd0000 - Port Control Command and Status Register */
  1334. char res10[12];
  1335. uint pcr; /* 0xd0010 - Port Configuration Register */
  1336. uint peir; /* 0xd0014 - Port Error Injection Register */
  1337. char res11[3048];
  1338. uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
  1339. char res12[12];
  1340. uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
  1341. char res13[12];
  1342. uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
  1343. char res14[4];
  1344. uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
  1345. char res15[4];
  1346. uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
  1347. char res16[12];
  1348. uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
  1349. char res17[4];
  1350. uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
  1351. char res18[4];
  1352. uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
  1353. char res19[12];
  1354. uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
  1355. char res20[4];
  1356. uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
  1357. char res21[4];
  1358. uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
  1359. char res22[12];
  1360. uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
  1361. char res23[4];
  1362. uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
  1363. char res24[4];
  1364. uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
  1365. char res25[12];
  1366. uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
  1367. char res26[4];
  1368. uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
  1369. char res27[4];
  1370. uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
  1371. char res28[12];
  1372. uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
  1373. char res29[4];
  1374. uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
  1375. char res30[4];
  1376. uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
  1377. char res31[12];
  1378. uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
  1379. char res32[4];
  1380. uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
  1381. char res33[4];
  1382. uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
  1383. char res34[12];
  1384. uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
  1385. char res35[4];
  1386. uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
  1387. char res36[4];
  1388. uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
  1389. char res37[76];
  1390. uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
  1391. char res38[4];
  1392. uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
  1393. char res39[4];
  1394. uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
  1395. char res40[12];
  1396. uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
  1397. char res41[4];
  1398. uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
  1399. char res42[4];
  1400. uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
  1401. char res43[12];
  1402. uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
  1403. char res44[4];
  1404. uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
  1405. char res45[4];
  1406. uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
  1407. char res46[12];
  1408. uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
  1409. char res47[4];
  1410. uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
  1411. char res48[4];
  1412. uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
  1413. char res49[12];
  1414. uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
  1415. char res50[12];
  1416. uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
  1417. char res51[12];
  1418. uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
  1419. uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
  1420. uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
  1421. uint pecr; /* 0xd0e0c - Port Error Control Register */
  1422. uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
  1423. uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
  1424. uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
  1425. char res52[4];
  1426. uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
  1427. char res53[4];
  1428. uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
  1429. uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
  1430. char res54[464];
  1431. uint omr; /* 0xd1000 - Outbound Mode Register */
  1432. uint osr; /* 0xd1004 - Outbound Status Register */
  1433. uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
  1434. uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
  1435. uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
  1436. uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
  1437. uint odpr; /* 0xd1018 - Outbound Destination Port Register */
  1438. uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
  1439. uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
  1440. uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
  1441. uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
  1442. char res55[52];
  1443. uint imr; /* 0xd1060 - Outbound Mode Register */
  1444. uint isr; /* 0xd1064 - Inbound Status Register */
  1445. uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
  1446. uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
  1447. uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
  1448. uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
  1449. char res56[1000];
  1450. uint dmr; /* 0xd1460 - Doorbell Mode Register */
  1451. uint dsr; /* 0xd1464 - Doorbell Status Register */
  1452. uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
  1453. uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
  1454. uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
  1455. uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
  1456. char res57[104];
  1457. uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
  1458. uint pwsr; /* 0xd14e4 - Port-Write Status Register */
  1459. uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
  1460. uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
  1461. char res58[60176];
  1462. } ccsr_rio_t;
  1463. /* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
  1464. typedef struct par_io {
  1465. uint cpodr; /* 0x100 */
  1466. uint cpdat; /* 0x104 */
  1467. uint cpdir1; /* 0x108 */
  1468. uint cpdir2; /* 0x10c */
  1469. uint cppar1; /* 0x110 */
  1470. uint cppar2; /* 0x114 */
  1471. char res[8];
  1472. }par_io_t;
  1473. /*
  1474. * Global Utilities Register Block(0xe_0000-0xf_ffff)
  1475. */
  1476. typedef struct ccsr_gur {
  1477. uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
  1478. #ifdef CONFIG_MPC8536
  1479. #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
  1480. #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
  1481. #else
  1482. #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
  1483. #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
  1484. #endif
  1485. #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
  1486. #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
  1487. uint porbmsr; /* 0xe0004 - POR boot mode status register */
  1488. #define MPC85xx_PORBMSR_HA 0x00070000
  1489. uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
  1490. uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
  1491. #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
  1492. #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
  1493. #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
  1494. #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
  1495. #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
  1496. #define MPC85xx_PORDEVSR_PCI1 0x00800000
  1497. #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
  1498. #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
  1499. #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
  1500. #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
  1501. #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
  1502. #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
  1503. #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
  1504. #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
  1505. #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
  1506. uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
  1507. uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
  1508. /* The 8544 RM says this is bit 26, but it's really bit 24 */
  1509. #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
  1510. char res1[8];
  1511. uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
  1512. char res2[12];
  1513. uint gpiocr; /* 0xe0030 - GPIO control register */
  1514. char res3[12];
  1515. #if defined(CONFIG_MPC8569)
  1516. uint plppar1;
  1517. /* 0xe0040 - Platform port pin assignment register 1 */
  1518. uint plppar2;
  1519. /* 0xe0044 - Platform port pin assignment register 2 */
  1520. uint plpdir1;
  1521. /* 0xe0048 - Platform port pin direction register 1 */
  1522. uint plpdir2;
  1523. /* 0xe004c - Platform port pin direction register 2 */
  1524. #else
  1525. uint gpoutdr; /* 0xe0040 - General-purpose output data register */
  1526. char res4[12];
  1527. #endif
  1528. uint gpindr; /* 0xe0050 - General-purpose input data register */
  1529. char res5[12];
  1530. uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
  1531. #define MPC85xx_PMUXCR_SD_DATA 0x80000000
  1532. #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
  1533. #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
  1534. char res6[12];
  1535. uint devdisr; /* 0xe0070 - Device disable control */
  1536. #define MPC85xx_DEVDISR_PCI1 0x80000000
  1537. #define MPC85xx_DEVDISR_PCI2 0x40000000
  1538. #define MPC85xx_DEVDISR_PCIE 0x20000000
  1539. #define MPC85xx_DEVDISR_LBC 0x08000000
  1540. #define MPC85xx_DEVDISR_PCIE2 0x04000000
  1541. #define MPC85xx_DEVDISR_PCIE3 0x02000000
  1542. #define MPC85xx_DEVDISR_SEC 0x01000000
  1543. #define MPC85xx_DEVDISR_SRIO 0x00080000
  1544. #define MPC85xx_DEVDISR_RMSG 0x00040000
  1545. #define MPC85xx_DEVDISR_DDR 0x00010000
  1546. #define MPC85xx_DEVDISR_CPU 0x00008000
  1547. #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
  1548. #define MPC85xx_DEVDISR_TB 0x00004000
  1549. #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
  1550. #define MPC85xx_DEVDISR_CPU1 0x00002000
  1551. #define MPC85xx_DEVDISR_TB1 0x00001000
  1552. #define MPC85xx_DEVDISR_DMA 0x00000400
  1553. #define MPC85xx_DEVDISR_TSEC1 0x00000080
  1554. #define MPC85xx_DEVDISR_TSEC2 0x00000040
  1555. #define MPC85xx_DEVDISR_TSEC3 0x00000020
  1556. #define MPC85xx_DEVDISR_TSEC4 0x00000010
  1557. #define MPC85xx_DEVDISR_I2C 0x00000004
  1558. #define MPC85xx_DEVDISR_DUART 0x00000002
  1559. char res7[12];
  1560. uint powmgtcsr; /* 0xe0080 - Power management status and control register */
  1561. char res8[12];
  1562. uint mcpsumr; /* 0xe0090 - Machine check summary register */
  1563. char res9[12];
  1564. uint pvr; /* 0xe00a0 - Processor version register */
  1565. uint svr; /* 0xe00a4 - System version register */
  1566. char res10a[8];
  1567. uint rstcr; /* 0xe00b0 - Reset control register */
  1568. #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
  1569. char res10b[76];
  1570. par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
  1571. char res10c[3136];
  1572. #else
  1573. char res10b[3404];
  1574. #endif
  1575. uint clkocr; /* 0xe0e00 - Clock out select register */
  1576. char res11[12];
  1577. uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
  1578. char res12[12];
  1579. uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
  1580. char res13[248];
  1581. uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
  1582. uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
  1583. uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
  1584. uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */
  1585. uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
  1586. char res15[61648]; /* 0xe0f30 to 0xefffff */
  1587. } ccsr_gur_t;
  1588. #define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
  1589. #define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
  1590. #define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
  1591. #define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
  1592. #define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
  1593. #define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
  1594. #define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
  1595. #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
  1596. #define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
  1597. #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
  1598. #define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000)
  1599. #define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
  1600. #define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
  1601. #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
  1602. #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
  1603. #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
  1604. #define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
  1605. #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
  1606. #define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
  1607. #define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
  1608. #define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000)
  1609. #define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
  1610. #define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000)
  1611. #define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
  1612. #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000)
  1613. #define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
  1614. #define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000)
  1615. #define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
  1616. #define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000)
  1617. #define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
  1618. #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000)
  1619. #define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
  1620. #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
  1621. #define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
  1622. #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
  1623. #define CONFIG_SYS_MPC85xx_USB_ADDR \
  1624. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
  1625. #endif /*__IMMAP_85xx__*/