canyonlands.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553
  1. /*
  2. * (C) Copyright 2008
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. #include <common.h>
  21. #include <ppc440.h>
  22. #include <libfdt.h>
  23. #include <fdt_support.h>
  24. #include <i2c.h>
  25. #include <asm/processor.h>
  26. #include <asm/io.h>
  27. #include <asm/mmu.h>
  28. #include <asm/4xx_pcie.h>
  29. #include <asm/gpio.h>
  30. #include <asm/errno.h>
  31. extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #define CONFIG_SYS_BCSR3_PCIE 0x10
  34. #define BOARD_CANYONLANDS_PCIE 1
  35. #define BOARD_CANYONLANDS_SATA 2
  36. #define BOARD_GLACIER 3
  37. #define BOARD_ARCHES 4
  38. /*
  39. * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
  40. * board specific values.
  41. */
  42. #if defined(CONFIG_ARCHES)
  43. u32 ddr_wrdtr(u32 default_val) {
  44. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
  45. }
  46. #else
  47. u32 ddr_wrdtr(u32 default_val) {
  48. return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
  49. }
  50. u32 ddr_clktr(u32 default_val) {
  51. return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
  52. }
  53. #endif
  54. #if defined(CONFIG_ARCHES)
  55. /*
  56. * FPGA read/write helper macros
  57. */
  58. static inline int board_fpga_read(int offset)
  59. {
  60. int data;
  61. data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
  62. return data;
  63. }
  64. static inline void board_fpga_write(int offset, int data)
  65. {
  66. out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
  67. }
  68. /*
  69. * CPLD read/write helper macros
  70. */
  71. static inline int board_cpld_read(int offset)
  72. {
  73. int data;
  74. out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  75. data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
  76. return data;
  77. }
  78. static inline void board_cpld_write(int offset, int data)
  79. {
  80. out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
  81. out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
  82. }
  83. #else
  84. static int pvr_460ex(void)
  85. {
  86. u32 pvr = get_pvr();
  87. if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
  88. (pvr == PVR_460EX_RB))
  89. return 1;
  90. return 0;
  91. }
  92. #endif /* defined(CONFIG_ARCHES) */
  93. int board_early_init_f(void)
  94. {
  95. #if !defined(CONFIG_ARCHES)
  96. u32 sdr0_cust0;
  97. #endif
  98. /*
  99. * Setup the interrupt controller polarities, triggers, etc.
  100. */
  101. mtdcr(UIC0SR, 0xffffffff); /* clear all */
  102. mtdcr(UIC0ER, 0x00000000); /* disable all */
  103. mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
  104. mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
  105. mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
  106. mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
  107. mtdcr(UIC0SR, 0xffffffff); /* clear all */
  108. mtdcr(UIC1SR, 0xffffffff); /* clear all */
  109. mtdcr(UIC1ER, 0x00000000); /* disable all */
  110. mtdcr(UIC1CR, 0x00000000); /* all non-critical */
  111. mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
  112. mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
  113. mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
  114. mtdcr(UIC1SR, 0xffffffff); /* clear all */
  115. mtdcr(UIC2SR, 0xffffffff); /* clear all */
  116. mtdcr(UIC2ER, 0x00000000); /* disable all */
  117. mtdcr(UIC2CR, 0x00000000); /* all non-critical */
  118. mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
  119. mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
  120. mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
  121. mtdcr(UIC2SR, 0xffffffff); /* clear all */
  122. mtdcr(UIC3SR, 0xffffffff); /* clear all */
  123. mtdcr(UIC3ER, 0x00000000); /* disable all */
  124. mtdcr(UIC3CR, 0x00000000); /* all non-critical */
  125. mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
  126. mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
  127. mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
  128. mtdcr(UIC3SR, 0xffffffff); /* clear all */
  129. #if !defined(CONFIG_ARCHES)
  130. /* SDR Setting - enable NDFC */
  131. mfsdr(SDR0_CUST0, sdr0_cust0);
  132. sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
  133. SDR0_CUST0_NDFC_ENABLE |
  134. SDR0_CUST0_NDFC_BW_8_BIT |
  135. SDR0_CUST0_NDFC_ARE_MASK |
  136. SDR0_CUST0_NDFC_BAC_ENCODE(3) |
  137. (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
  138. mtsdr(SDR0_CUST0, sdr0_cust0);
  139. #endif
  140. /*
  141. * Configure PFC (Pin Function Control) registers
  142. * UART0: 4 pins
  143. */
  144. mtsdr(SDR0_PFC1, 0x00040000);
  145. /* Enable PCI host functionality in SDR0_PCI0 */
  146. mtsdr(SDR0_PCI0, 0xe0000000);
  147. #if !defined(CONFIG_ARCHES)
  148. /* Enable ethernet and take out of reset */
  149. out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
  150. /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
  151. out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
  152. /* Enable USB host & USB-OTG */
  153. out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
  154. mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
  155. /* Setup PLB4-AHB bridge based on the system address map */
  156. mtdcr(AHB_TOP, 0x8000004B);
  157. mtdcr(AHB_BOT, 0x8000004B);
  158. if (pvr_460ex()) {
  159. /*
  160. * Configure USB-STP pins as alternate and not GPIO
  161. * It seems to be neccessary to configure the STP pins as GPIO
  162. * input at powerup (perhaps while USB reset is asserted). So
  163. * we configure those pins to their "real" function now.
  164. */
  165. gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
  166. gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
  167. }
  168. #endif
  169. return 0;
  170. }
  171. #if !defined(CONFIG_ARCHES)
  172. static void canyonlands_sata_init(int board_type)
  173. {
  174. u32 reg;
  175. if (board_type == BOARD_CANYONLANDS_SATA) {
  176. /* Put SATA in reset */
  177. SDR_WRITE(SDR0_SRST1, 0x00020001);
  178. /* Set the phy for SATA, not PCI-E port 0 */
  179. reg = SDR_READ(PESDR0_PHY_CTL_RST);
  180. SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
  181. reg = SDR_READ(PESDR0_L0CLK);
  182. SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
  183. SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
  184. SDR_WRITE(PESDR0_L0DRV, 0x00000104);
  185. /* Bring SATA out of reset */
  186. SDR_WRITE(SDR0_SRST1, 0x00000000);
  187. }
  188. }
  189. #endif /* !defined(CONFIG_ARCHES) */
  190. int get_cpu_num(void)
  191. {
  192. int cpu = NA_OR_UNKNOWN_CPU;
  193. #if defined(CONFIG_ARCHES)
  194. int cpu_num;
  195. cpu_num = board_fpga_read(0x3);
  196. /* sanity check; assume cpu numbering starts and increments from 0 */
  197. if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
  198. cpu = cpu_num;
  199. #endif
  200. return cpu;
  201. }
  202. #if !defined(CONFIG_ARCHES)
  203. int checkboard(void)
  204. {
  205. char *s = getenv("serial#");
  206. if (pvr_460ex()) {
  207. printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
  208. if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
  209. gd->board_type = BOARD_CANYONLANDS_PCIE;
  210. else
  211. gd->board_type = BOARD_CANYONLANDS_SATA;
  212. } else {
  213. printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
  214. gd->board_type = BOARD_GLACIER;
  215. }
  216. switch (gd->board_type) {
  217. case BOARD_CANYONLANDS_PCIE:
  218. case BOARD_GLACIER:
  219. puts(", 2*PCIe");
  220. break;
  221. case BOARD_CANYONLANDS_SATA:
  222. puts(", 1*PCIe/1*SATA");
  223. break;
  224. }
  225. printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
  226. if (s != NULL) {
  227. puts(", serial# ");
  228. puts(s);
  229. }
  230. putc('\n');
  231. canyonlands_sata_init(gd->board_type);
  232. return (0);
  233. }
  234. #else /* defined(CONFIG_ARCHES) */
  235. int checkboard(void)
  236. {
  237. char *s = getenv("serial#");
  238. printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
  239. printf(" Revision %02x.%02x ",
  240. board_fpga_read(0x0), board_fpga_read(0x1));
  241. gd->board_type = BOARD_ARCHES;
  242. /* Only CPU0 has access to CPLD registers */
  243. if (get_cpu_num() == 0) {
  244. u8 cfg_sw = board_cpld_read(0x1);
  245. printf("(FPGA=%02x, CPLD=%02x)\n",
  246. board_fpga_read(0x2), board_cpld_read(0x0));
  247. printf(" Configuration Switch %d%d%d%d\n",
  248. ((cfg_sw >> 3) & 0x01),
  249. ((cfg_sw >> 2) & 0x01),
  250. ((cfg_sw >> 1) & 0x01),
  251. ((cfg_sw >> 0) & 0x01));
  252. } else
  253. printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
  254. if (s != NULL)
  255. printf(" Serial# %s\n", s);
  256. return 0;
  257. }
  258. #endif /* !defined(CONFIG_ARCHES) */
  259. #if defined(CONFIG_NAND_U_BOOT)
  260. /*
  261. * NAND booting U-Boot version uses a fixed initialization, since the whole
  262. * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
  263. * code.
  264. */
  265. phys_size_t initdram(int board_type)
  266. {
  267. return CONFIG_SYS_MBYTES_SDRAM << 20;
  268. }
  269. #endif
  270. /*
  271. * pci_target_init
  272. *
  273. * The bootstrap configuration provides default settings for the pci
  274. * inbound map (PIM). But the bootstrap config choices are limited and
  275. * may not be sufficient for a given board.
  276. */
  277. #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
  278. void pci_target_init(struct pci_controller * hose )
  279. {
  280. /*
  281. * Disable everything
  282. */
  283. out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
  284. out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
  285. out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
  286. out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
  287. /*
  288. * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
  289. * strapping options to not support sizes such as 128/256 MB.
  290. */
  291. out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
  292. out_le32((void *)PCIL0_PIM0LAH, 0);
  293. out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
  294. out_le32((void *)PCIL0_BAR0, 0);
  295. /*
  296. * Program the board's subsystem id/vendor id
  297. */
  298. out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
  299. out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
  300. out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
  301. }
  302. #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
  303. #if defined(CONFIG_PCI)
  304. /*
  305. * is_pci_host
  306. *
  307. * This routine is called to determine if a pci scan should be
  308. * performed. With various hardware environments (especially cPCI and
  309. * PPMC) it's insufficient to depend on the state of the arbiter enable
  310. * bit in the strap register, or generic host/adapter assumptions.
  311. *
  312. * Rather than hard-code a bad assumption in the general 440 code, the
  313. * 440 pci code requires the board to decide at runtime.
  314. *
  315. * Return 0 for adapter mode, non-zero for host (monarch) mode.
  316. */
  317. int is_pci_host(struct pci_controller *hose)
  318. {
  319. /* Board is always configured as host. */
  320. return (1);
  321. }
  322. int board_pcie_first(void)
  323. {
  324. /*
  325. * Canyonlands with SATA enabled has only one PCIe slot
  326. * (2nd one).
  327. */
  328. if (gd->board_type == BOARD_CANYONLANDS_SATA)
  329. return 1;
  330. return 0;
  331. }
  332. #endif /* CONFIG_PCI */
  333. int board_early_init_r (void)
  334. {
  335. /*
  336. * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
  337. * boot EBC mapping only supports a maximum of 16MBytes
  338. * (4.ff00.0000 - 4.ffff.ffff).
  339. * To solve this problem, the FLASH has to get remapped to another
  340. * EBC address which accepts bigger regions:
  341. *
  342. * 0xfc00.0000 -> 4.cc00.0000
  343. */
  344. /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
  345. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  346. mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
  347. #else
  348. mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
  349. #endif
  350. /* Remove TLB entry of boot EBC mapping */
  351. remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
  352. /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
  353. program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
  354. TLB_WORD2_I_ENABLE);
  355. /*
  356. * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
  357. * 0xfc00.0000 is possible
  358. */
  359. /*
  360. * Clear potential errors resulting from auto-calibration.
  361. * If not done, then we could get an interrupt later on when
  362. * exceptions are enabled.
  363. */
  364. set_mcsr(get_mcsr());
  365. return 0;
  366. }
  367. #if !defined(CONFIG_ARCHES)
  368. int misc_init_r(void)
  369. {
  370. u32 sdr0_srst1 = 0;
  371. u32 eth_cfg;
  372. u8 val;
  373. /*
  374. * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
  375. * This is board specific, so let's do it here.
  376. */
  377. mfsdr(SDR0_ETH_CFG, eth_cfg);
  378. /* disable SGMII mode */
  379. eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
  380. SDR0_ETH_CFG_SGMII1_ENABLE |
  381. SDR0_ETH_CFG_SGMII0_ENABLE);
  382. /* Set the for 2 RGMII mode */
  383. /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
  384. eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
  385. if (pvr_460ex())
  386. eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  387. else
  388. eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
  389. mtsdr(SDR0_ETH_CFG, eth_cfg);
  390. /*
  391. * The AHB Bridge core is held in reset after power-on or reset
  392. * so enable it now
  393. */
  394. mfsdr(SDR0_SRST1, sdr0_srst1);
  395. sdr0_srst1 &= ~SDR0_SRST1_AHB;
  396. mtsdr(SDR0_SRST1, sdr0_srst1);
  397. /*
  398. * RTC/M41T62:
  399. * Disable square wave output: Batterie will be drained
  400. * quickly, when this output is not disabled
  401. */
  402. val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
  403. val &= ~0x40;
  404. i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
  405. return 0;
  406. }
  407. #else /* defined(CONFIG_ARCHES) */
  408. int misc_init_r(void)
  409. {
  410. u32 eth_cfg = 0;
  411. u32 eth_pll;
  412. u32 reg;
  413. /*
  414. * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
  415. * This is board specific, so let's do it here.
  416. */
  417. /* enable SGMII mode */
  418. eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
  419. SDR0_ETH_CFG_SGMII1_ENABLE |
  420. SDR0_ETH_CFG_SGMII2_ENABLE);
  421. /* Set EMAC for MDIO */
  422. eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
  423. /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
  424. eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
  425. mtsdr(SDR0_ETH_CFG, eth_cfg);
  426. /* reset all SGMII interfaces */
  427. mfsdr(SDR0_SRST1, reg);
  428. reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
  429. mtsdr(SDR0_SRST1, reg);
  430. mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
  431. mtsdr(SDR0_SRST1, 0x00000000);
  432. do {
  433. mfsdr(SDR0_ETH_PLL, eth_pll);
  434. } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
  435. return 0;
  436. }
  437. #endif /* !defined(CONFIG_ARCHES) */
  438. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  439. extern void __ft_board_setup(void *blob, bd_t *bd);
  440. void ft_board_setup(void *blob, bd_t *bd)
  441. {
  442. __ft_board_setup(blob, bd);
  443. if (gd->board_type == BOARD_CANYONLANDS_SATA) {
  444. /*
  445. * When SATA is selected we need to disable the first PCIe
  446. * node in the device tree, so that Linux doesn't initialize
  447. * it.
  448. */
  449. fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
  450. "disabled", sizeof("disabled"), 1);
  451. }
  452. if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
  453. /*
  454. * When PCIe is selected we need to disable the SATA
  455. * node in the device tree, so that Linux doesn't initialize
  456. * it.
  457. */
  458. fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
  459. "disabled", sizeof("disabled"), 1);
  460. }
  461. }
  462. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */