bf526-ezbrd.h 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188
  1. /*
  2. * U-boot - Configuration file for BF526 EZBrd board
  3. */
  4. #ifndef __CONFIG_BF526_EZBRD_H__
  5. #define __CONFIG_BF526_EZBRD_H__
  6. #include <asm/config-pre.h>
  7. /*
  8. * Processor Settings
  9. */
  10. #define CONFIG_BFIN_CPU bf526-0.0
  11. #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
  12. /*
  13. * Clock Settings
  14. * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  15. * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  16. */
  17. /* CONFIG_CLKIN_HZ is any value in Hz */
  18. #define CONFIG_CLKIN_HZ 25000000
  19. /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
  20. /* 1 = CLKIN / 2 */
  21. #define CONFIG_CLKIN_HALF 0
  22. /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
  23. /* 1 = bypass PLL */
  24. #define CONFIG_PLL_BYPASS 0
  25. /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
  26. /* Values can range from 0-63 (where 0 means 64) */
  27. #define CONFIG_VCO_MULT 16
  28. /* CCLK_DIV controls the core clock divider */
  29. /* Values can be 1, 2, 4, or 8 ONLY */
  30. #define CONFIG_CCLK_DIV 1
  31. /* SCLK_DIV controls the system clock divider */
  32. /* Values can range from 1-15 */
  33. #define CONFIG_SCLK_DIV 5
  34. /*
  35. * Memory Settings
  36. */
  37. /* This board has a 64meg MT48H32M16 */
  38. #define CONFIG_MEM_ADD_WDTH 10
  39. #define CONFIG_MEM_SIZE 64
  40. #define CONFIG_EBIU_SDRRC_VAL 0x0267
  41. #define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS)
  42. #define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
  43. #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
  44. #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
  45. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  46. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  47. /*
  48. * NAND Settings
  49. * (can't be used same time as ethernet)
  50. */
  51. #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
  52. #define CONFIG_BFIN_NFC
  53. #endif
  54. #ifdef CONFIG_BFIN_NFC
  55. #define CONFIG_BFIN_NFC_CTL_VAL 0x0033
  56. #define CONFIG_DRIVER_NAND_BFIN
  57. #define CONFIG_SYS_NAND_BASE 0 /* not actually used */
  58. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  59. #define NAND_MAX_CHIPS 1
  60. #define CONFIG_CMD_NAND
  61. #endif
  62. /*
  63. * Network Settings
  64. */
  65. #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
  66. !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
  67. #define ADI_CMDS_NETWORK 1
  68. #define CONFIG_BFIN_MAC
  69. #define CONFIG_RMII
  70. #define CONFIG_NETCONSOLE 1
  71. #define CONFIG_NET_MULTI 1
  72. #endif
  73. #define CONFIG_HOSTNAME bf526-ezbrd
  74. /* Uncomment next line to use fixed MAC address */
  75. /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
  76. /*
  77. * Flash Settings
  78. */
  79. #define CONFIG_FLASH_CFI_DRIVER
  80. #define CONFIG_SYS_FLASH_BASE 0x20000000
  81. #define CONFIG_SYS_FLASH_CFI
  82. #define CONFIG_SYS_FLASH_PROTECTION
  83. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  84. #define CONFIG_SYS_MAX_FLASH_SECT 71
  85. /*
  86. * SPI Settings
  87. */
  88. #define CONFIG_BFIN_SPI
  89. #define CONFIG_ENV_SPI_MAX_HZ 30000000
  90. #define CONFIG_SF_DEFAULT_SPEED 30000000
  91. #define CONFIG_SPI_FLASH
  92. #define CONFIG_SPI_FLASH_SST
  93. /*
  94. * Env Storage Settings
  95. */
  96. #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
  97. #define CONFIG_ENV_IS_IN_SPI_FLASH
  98. #define CONFIG_ENV_OFFSET 0x4000
  99. #define CONFIG_ENV_SIZE 0x2000
  100. #define CONFIG_ENV_SECT_SIZE 0x2000
  101. #else
  102. #define CONFIG_ENV_IS_IN_FLASH
  103. #define CONFIG_ENV_OFFSET 0x4000
  104. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
  105. #define CONFIG_ENV_SIZE 0x2000
  106. #define CONFIG_ENV_SECT_SIZE 0x2000
  107. #endif
  108. #define ENV_IS_EMBEDDED_CUSTOM
  109. /*
  110. * I2C Settings
  111. */
  112. #define CONFIG_BFIN_TWI_I2C 1
  113. #define CONFIG_HARD_I2C 1
  114. #define CONFIG_SYS_I2C_SPEED 50000
  115. #define CONFIG_SYS_I2C_SLAVE 0
  116. /*
  117. * USB Settings
  118. */
  119. #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
  120. #define CONFIG_USB
  121. #define CONFIG_MUSB_HCD
  122. #define CONFIG_USB_BLACKFIN
  123. #define CONFIG_USB_STORAGE
  124. #define CONFIG_MUSB_TIMEOUT 100000
  125. #endif
  126. /*
  127. * Misc Settings
  128. */
  129. #define CONFIG_MISC_INIT_R
  130. #define CONFIG_RTC_BFIN
  131. #define CONFIG_UART_CONSOLE 1
  132. /* define to enable run status via led */
  133. /* #define CONFIG_STATUS_LED */
  134. #ifdef CONFIG_STATUS_LED
  135. #define CONFIG_BOARD_SPECIFIC_LED
  136. #ifndef __ASSEMBLY__
  137. typedef unsigned int led_id_t;
  138. void __led_init(led_id_t mask, int state);
  139. void __led_set(led_id_t mask, int state);
  140. void __led_toggle(led_id_t mask);
  141. #endif
  142. /* use LED0 to indicate booting/alive */
  143. #define STATUS_LED_BOOT 0
  144. #define STATUS_LED_BIT 1
  145. #define STATUS_LED_STATE STATUS_LED_ON
  146. #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
  147. /* use LED1 to indicate crash */
  148. #define STATUS_LED_CRASH 1
  149. #define STATUS_LED_BIT1 2
  150. #define STATUS_LED_STATE1 STATUS_LED_ON
  151. #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
  152. #endif
  153. /*
  154. * Pull in common ADI header for remaining command/environment setup
  155. */
  156. #include <configs/bfin_adi_common.h>
  157. #endif