vovpn-gw.c 16 KB

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  1. /*
  2. * (C) Copyright 2004
  3. * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
  4. *
  5. * Support for the Elmeg VoVPN Gateway Module
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <ioports.h>
  24. #include <mpc8260.h>
  25. #include <asm/m8260_pci.h>
  26. #include <miiphy.h>
  27. #include "m88e6060.h"
  28. /*
  29. * I/O Port configuration table
  30. *
  31. * if conf is 1, then that port pin will be configured at boot time
  32. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  33. */
  34. const iop_conf_t iop_conf_tab[4][32] = {
  35. /* Port A configuration */
  36. { /* conf ppar psor pdir podr pdat */
  37. /* PA31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1252 */
  38. /* PA30 */ { 1, 0, 0, 0, 0, 0 }, /* GPI BP_RES */
  39. /* PA29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1253 */
  40. /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 RMII TX_EN */
  41. /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII CRS_DV */
  42. /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RMII RX_ERR */
  43. /* PA25 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  44. /* PA24 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  45. /* PA23 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  46. /* PA22 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  47. /* PA21 */ { 1, 0, 0, 0, 0, 0 }, /* GPI HWID */
  48. /* PA20 */ { 1, 0, 0, 1, 0, 1 }, /* GPO LED STATUS */
  49. /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[1] */
  50. /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 RMII TxD[0] */
  51. /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[0] */
  52. /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RMII RxD[1] */
  53. /* PA15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1255 */
  54. /* PA14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP???? */
  55. /* PA13 */ { 1, 0, 0, 1, 0, 1 }, /* GPO EN_BCTL1 XXX jse */
  56. /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* GPO SWITCH RESET */
  57. /* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL1 RESET */
  58. /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO DSP SL2 RESET */
  59. /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
  60. /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
  61. /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  62. /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  63. /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  64. /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  65. /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  66. /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  67. /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exit */
  68. /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exit */
  69. },
  70. /* Port B configuration */
  71. { /* conf ppar psor pdir podr pdat */
  72. /* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1257 */
  73. /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII CRS_DV */
  74. /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 RMII TX_EN */
  75. /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RX_ERR */
  76. /* PB27 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1TXD XXX val=0 */
  77. /* PB26 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_B2 L1RXD XXX val,dr */
  78. /* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1259 */
  79. /* PB24 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B2 L1RSYNC */
  80. /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[1] */
  81. /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 RMII TxD[0] */
  82. /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[0] */
  83. /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 RMII RxD[1] */
  84. /* PB19 */ { 1, 0, 0, 1, 0, 1 }, /* GPO PHY MDC */
  85. /* PB18 */ { 1, 0, 0, 0, 0, 0 }, /* GPIO PHY MDIO */
  86. /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  87. /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  88. /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  89. /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  90. /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  91. /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  92. /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  93. /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  94. /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  95. /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  96. /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  97. /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  98. /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  99. /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  100. /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  101. /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  102. /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  103. /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
  104. },
  105. /* Port C */
  106. { /* conf ppar psor pdir podr pdat */
  107. /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  108. /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  109. /* PC29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1183 */
  110. /* PC28 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1184 */
  111. /* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* CLK5 TDM_A1 RX */
  112. /* PC26 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1185 */
  113. /* PC25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1178 */
  114. /* PC24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1186 */
  115. /* PC23 */ { 1, 1, 0, 0, 0, 0 }, /* CLK9 TDM_B2 RX */
  116. /* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* CLK10 FCC1 RMII REFCLK */
  117. /* PC21 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1187 */
  118. /* PC20 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1182 */
  119. /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1188 */
  120. /* PC18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO HW RESET */
  121. /* PC17 */ { 1, 1, 0, 1, 0, 0 }, /* BRG8 SWITCH CLKIN */
  122. /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* CLK16 FCC2 RMII REFCLK */
  123. /* PC15 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_3 */
  124. /* PC14 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_2 */
  125. /* PC13 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_1 */
  126. /* PC12 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL1_MTYPE_0 */
  127. /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1176 */
  128. /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1177 */
  129. /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_3 */
  130. /* PC8 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_2 */
  131. /* PC7 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_1 */
  132. /* PC6 */ { 1, 0, 0, 0, 0, 0 }, /* GPI SL2_MTYPE_0 */
  133. /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  134. /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  135. /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  136. /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  137. /* PC1 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1192 */
  138. /* PC0 */ { 1, 0, 0, 0, 0, 0 }, /* GPI RACK */
  139. },
  140. /* Port D */
  141. { /* conf ppar psor pdir podr pdat */
  142. /* PD31 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1193 */
  143. /* PD30 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1194 */
  144. /* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1195 */
  145. /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  146. /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  147. /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  148. /* PD25 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1179 */
  149. /* PD24 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1180 */
  150. /* PD23 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1181 */
  151. /* PD22 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1TXD */
  152. /* PD21 */ { 1, 1, 1, 0, 1, 0 }, /* TDM_A2 L1RXD */
  153. /* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
  154. /* PD19 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1196 */
  155. /* PD18 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1197 */
  156. /* PD17 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1198 */
  157. /* PD16 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1199 */
  158. /* PD15 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1250 */
  159. /* PD14 */ { 1, 0, 0, 1, 0, 0 }, /* GPO TP1251 */
  160. /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  161. /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  162. /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  163. /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  164. /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  165. /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  166. /* PD7 */ { 0, 0, 0, 1, 0, 0 }, /* GPO FL_BYTE */
  167. /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  168. /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  169. /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  170. /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  171. /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  172. /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin does not exist */
  173. /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin does not exist */
  174. }
  175. };
  176. void reset_phy (void)
  177. {
  178. volatile ioport_t *iop;
  179. #if defined(CONFIG_CMD_NET)
  180. int i;
  181. unsigned short val;
  182. #endif
  183. iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
  184. /* Reset the PHY */
  185. iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */
  186. #if defined(CONFIG_CMD_NET)
  187. udelay(20000);
  188. iop->pdat |= 0x00080000;
  189. for (i=0; i<100; i++) {
  190. udelay(20000);
  191. if (bb_miiphy_read("FCC1", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) {
  192. break;
  193. }
  194. }
  195. /* initialize switch */
  196. m88e6060_initialize( CONFIG_SYS_PHY_ADDR );
  197. #endif
  198. }
  199. static unsigned long UPMATable[] = {
  200. 0x8fffec00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */
  201. 0x0ffcfc04, 0x3ffdfc00, 0xfffffc01, 0xfffffc01, /* Words 4 to 7 */
  202. 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 8 to 11 */
  203. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 12 to 15 */
  204. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 16 to 19 */
  205. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
  206. 0x8fffec00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */
  207. 0x0ffffc04, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
  208. 0xfffffc00, 0xfffffc01, 0xfffffc01, 0xfffffc00, /* Words 32 to 35 */
  209. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 36 to 39 */
  210. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
  211. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
  212. 0xfffffc00, 0xfffffc04, 0xfffffc01, 0xfffffc00, /* Words 48 to 51 */
  213. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
  214. 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
  215. 0xffffec00, 0xffffec04, 0xffffec00, 0xfffffc01 /* Words 60 to 63 */
  216. };
  217. int board_early_init_f (void)
  218. {
  219. volatile immap_t *immap;
  220. volatile memctl8260_t *memctl;
  221. volatile unsigned char *dummy;
  222. int i;
  223. immap = (immap_t *) CONFIG_SYS_IMMR;
  224. memctl = &immap->im_memctl;
  225. #if 0
  226. /* CS2-5 - DSP via UPMA */
  227. dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
  228. memctl->memc_mar = 0;
  229. memctl->memc_mamr = MxMR_OP_WARR;
  230. for (i = 0; i < 64; i++) {
  231. memctl->memc_mdr = UPMATable[i];
  232. *dummy = 0;
  233. }
  234. memctl->memc_mamr = 0x00044440;
  235. #else
  236. /* CS7 - DPRAM via UPMA */
  237. dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
  238. memctl->memc_mar = 0;
  239. memctl->memc_mamr = MxMR_OP_WARR;
  240. for (i = 0; i < 64; i++) {
  241. memctl->memc_mdr = UPMATable[i];
  242. *dummy = 0;
  243. }
  244. memctl->memc_mamr = 0x00044440;
  245. #endif
  246. return 0;
  247. }
  248. int misc_init_r (void)
  249. {
  250. volatile ioport_t *iop;
  251. unsigned char temp;
  252. #if 0
  253. /* DUMP UPMA RAM */
  254. volatile immap_t *immap;
  255. volatile memctl8260_t *memctl;
  256. volatile unsigned char *dummy;
  257. unsigned char c;
  258. int i;
  259. immap = (immap_t *) CONFIG_SYS_IMMR;
  260. memctl = &immap->im_memctl;
  261. dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
  262. memctl->memc_mar = 0;
  263. memctl->memc_mamr = MxMR_OP_RARR;
  264. for (i = 0; i < 64; i++) {
  265. c = *dummy;
  266. printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
  267. memctl->memc_mamr,
  268. memctl->memc_mar,
  269. memctl->memc_mdr );
  270. }
  271. memctl->memc_mamr = 0x00044440;
  272. #endif
  273. /* enable buffers (DSP, DPRAM) */
  274. iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
  275. iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */
  276. /* destroy DPRAM magic */
  277. *(volatile unsigned char *)0xf0500000 = 0x00;
  278. /* clear any pending DPRAM irq */
  279. temp = *(volatile unsigned char *)0xf05003ff;
  280. /* write module-id into DPRAM */
  281. *(volatile unsigned char *)0xf0500201 = 0x50;
  282. return 0;
  283. }
  284. #if defined(CONFIG_HAVE_OWN_RESET)
  285. int
  286. do_reset (void *cmdtp, int flag, int argc, char * const argv[])
  287. {
  288. volatile ioport_t *iop;
  289. iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2);
  290. iop->pdat |= 0x00002000; /* PC18 = HW_RESET */
  291. return 1;
  292. }
  293. #endif /* CONFIG_HAVE_OWN_RESET */
  294. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
  295. phys_size_t initdram (int board_type)
  296. {
  297. #ifndef CONFIG_SYS_RAMBOOT
  298. volatile immap_t *immap;
  299. volatile memctl8260_t *memctl;
  300. volatile uchar *ramaddr;
  301. int i;
  302. uchar c;
  303. immap = (immap_t *) CONFIG_SYS_IMMR;
  304. memctl = &immap->im_memctl;
  305. ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
  306. c = 0xff;
  307. immap->im_siu_conf.sc_ppc_acr = 0x02;
  308. immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
  309. immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
  310. immap->im_siu_conf.sc_tescr1 = 0x00000000;
  311. immap->im_siu_conf.sc_tescr2 = 0x00000000;
  312. memctl->memc_mptpr = CONFIG_SYS_MPTPR;
  313. memctl->memc_psrt = CONFIG_SYS_PSRT;
  314. memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
  315. memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM;
  316. /* Precharge all banks */
  317. memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
  318. *ramaddr = c;
  319. /* CBR refresh */
  320. memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
  321. for (i = 0; i < 8; i++)
  322. *ramaddr = c;
  323. /* Mode Register write */
  324. memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
  325. *ramaddr = c;
  326. /* Refresh enable */
  327. memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
  328. *ramaddr = c;
  329. #endif /* CONFIG_SYS_RAMBOOT */
  330. return (CONFIG_SYS_SDRAM_SIZE);
  331. }
  332. int checkboard (void)
  333. {
  334. #ifdef CONFIG_CLKIN_66MHz
  335. puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
  336. #else
  337. puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
  338. #endif
  339. return 0;
  340. }