cpu.c 3.6 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. /*
  25. * CPU test
  26. *
  27. * This test checks the arithmetic logic unit (ALU) of CPU.
  28. * It tests independently various groups of instructions using
  29. * run-time modification of the code to reduce the memory footprint.
  30. * For more details refer to post/cpu/ *.c files.
  31. */
  32. #ifdef CONFIG_POST
  33. #include <watchdog.h>
  34. #include <post.h>
  35. #include <asm/mmu.h>
  36. #if CONFIG_POST & CFG_POST_CPU
  37. extern int cpu_post_test_cmp (void);
  38. extern int cpu_post_test_cmpi (void);
  39. extern int cpu_post_test_two (void);
  40. extern int cpu_post_test_twox (void);
  41. extern int cpu_post_test_three (void);
  42. extern int cpu_post_test_threex (void);
  43. extern int cpu_post_test_threei (void);
  44. extern int cpu_post_test_andi (void);
  45. extern int cpu_post_test_srawi (void);
  46. extern int cpu_post_test_rlwnm (void);
  47. extern int cpu_post_test_rlwinm (void);
  48. extern int cpu_post_test_rlwimi (void);
  49. extern int cpu_post_test_store (void);
  50. extern int cpu_post_test_load (void);
  51. extern int cpu_post_test_cr (void);
  52. extern int cpu_post_test_b (void);
  53. extern int cpu_post_test_multi (void);
  54. extern int cpu_post_test_string (void);
  55. extern int cpu_post_test_complex (void);
  56. DECLARE_GLOBAL_DATA_PTR;
  57. ulong cpu_post_makecr (long v)
  58. {
  59. ulong cr = 0;
  60. if (v < 0)
  61. cr |= 0x80000000;
  62. if (v > 0)
  63. cr |= 0x40000000;
  64. if (v == 0)
  65. cr |= 0x20000000;
  66. return cr;
  67. }
  68. int cpu_post_test (int flags)
  69. {
  70. int ic = icache_status ();
  71. int ret = 0;
  72. WATCHDOG_RESET();
  73. if (ic)
  74. icache_disable ();
  75. #ifdef CONFIG_4xx_DCACHE
  76. /* disable cache */
  77. change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
  78. #endif
  79. if (ret == 0)
  80. ret = cpu_post_test_cmp ();
  81. if (ret == 0)
  82. ret = cpu_post_test_cmpi ();
  83. if (ret == 0)
  84. ret = cpu_post_test_two ();
  85. if (ret == 0)
  86. ret = cpu_post_test_twox ();
  87. WATCHDOG_RESET();
  88. if (ret == 0)
  89. ret = cpu_post_test_three ();
  90. if (ret == 0)
  91. ret = cpu_post_test_threex ();
  92. if (ret == 0)
  93. ret = cpu_post_test_threei ();
  94. if (ret == 0)
  95. ret = cpu_post_test_andi ();
  96. WATCHDOG_RESET();
  97. if (ret == 0)
  98. ret = cpu_post_test_srawi ();
  99. if (ret == 0)
  100. ret = cpu_post_test_rlwnm ();
  101. if (ret == 0)
  102. ret = cpu_post_test_rlwinm ();
  103. if (ret == 0)
  104. ret = cpu_post_test_rlwimi ();
  105. WATCHDOG_RESET();
  106. if (ret == 0)
  107. ret = cpu_post_test_store ();
  108. if (ret == 0)
  109. ret = cpu_post_test_load ();
  110. if (ret == 0)
  111. ret = cpu_post_test_cr ();
  112. if (ret == 0)
  113. ret = cpu_post_test_b ();
  114. WATCHDOG_RESET();
  115. if (ret == 0)
  116. ret = cpu_post_test_multi ();
  117. WATCHDOG_RESET();
  118. if (ret == 0)
  119. ret = cpu_post_test_string ();
  120. if (ret == 0)
  121. ret = cpu_post_test_complex ();
  122. WATCHDOG_RESET();
  123. if (ic)
  124. icache_enable ();
  125. #ifdef CONFIG_4xx_DCACHE
  126. /* enable cache */
  127. change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
  128. #endif
  129. WATCHDOG_RESET();
  130. return ret;
  131. }
  132. #endif /* CONFIG_POST & CFG_POST_CPU */
  133. #endif /* CONFIG_POST */