bfin_mac.h 2.6 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889
  1. /*
  2. * bfin_mac.h - some defines/structures for the Blackfin on-chip MAC.
  3. *
  4. * Copyright (c) 2005-2008 Analog Device, Inc.
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #ifndef __BFIN_MAC_H__
  9. #define __BFIN_MAC_H__
  10. #define PHYADDR 0x01
  11. #define NO_PHY_REGS 0x20
  12. #define DEFAULT_PHY_PHYID1 0x0007
  13. #define DEFAULT_PHY_PHYID2 0xC0A3
  14. #define PHY_MODECTL 0x00
  15. #define PHY_MODESTAT 0x01
  16. #define PHY_PHYID1 0x02
  17. #define PHY_PHYID2 0x03
  18. #define PHY_ANAR 0x04
  19. #define PHY_ANLPAR 0x05
  20. #define PHY_ANER 0x06
  21. #define PHY_RESET 0x8000
  22. #define PHY_ANEG_EN 0x1000
  23. #define PHY_DUPLEX 0x0100
  24. #define PHY_SPD_SET 0x2000
  25. #define RECV_BUFSIZE (0x614)
  26. typedef volatile u32 reg32;
  27. typedef volatile u16 reg16;
  28. typedef struct ADI_DMA_CONFIG_REG {
  29. u16 b_DMA_EN:1; /* 0 Enabled */
  30. u16 b_WNR:1; /* 1 Direction */
  31. u16 b_WDSIZE:2; /* 2:3 Transfer word size */
  32. u16 b_DMA2D:1; /* 4 DMA mode */
  33. u16 b_RESTART:1; /* 5 Retain FIFO */
  34. u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
  35. u16 b_DI_EN:1; /* 7 Data interrupt enabled */
  36. u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
  37. u16 b_FLOW:3; /* 12:14Flow */
  38. } ADI_DMA_CONFIG_REG;
  39. typedef struct adi_ether_frame_buffer {
  40. u16 NoBytes; /* the no. of following bytes */
  41. u8 Dest[6]; /* destination MAC address */
  42. u8 Srce[6]; /* source MAC address */
  43. u16 LTfield; /* length/type field */
  44. u8 Data[0]; /* payload bytes */
  45. } ADI_ETHER_FRAME_BUFFER;
  46. /* 16 bytes/struct */
  47. typedef struct dma_descriptor {
  48. struct dma_descriptor *NEXT_DESC_PTR;
  49. u32 START_ADDR;
  50. ADI_DMA_CONFIG_REG CONFIG;
  51. } DMA_DESCRIPTOR;
  52. /* 10 bytes/struct in 12 bytes */
  53. typedef struct adi_ether_buffer {
  54. DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
  55. ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
  56. struct adi_ether_buffer *pNext; /* next buffer */
  57. struct adi_ether_buffer *pPrev; /* prev buffer */
  58. u16 IPHdrChksum; /* the IP header checksum */
  59. u16 IPPayloadChksum; /* the IP header and payload checksum */
  60. volatile u32 StatusWord; /* the frame status word */
  61. } ADI_ETHER_BUFFER;
  62. /* 40 bytes/struct in 44 bytes */
  63. static ADI_ETHER_BUFFER *SetupRxBuffer(int no);
  64. static ADI_ETHER_BUFFER *SetupTxBuffer(int no);
  65. static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd);
  66. static void bfin_EMAC_halt(struct eth_device *dev);
  67. static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length);
  68. static int bfin_EMAC_recv(struct eth_device *dev);
  69. static void PollMdcDone(void);
  70. static void WrPHYReg(u16 PHYAddr, u16 RegAddr, u16 Data);
  71. static u16 RdPHYReg(u16 PHYAddr, u16 RegAddr);
  72. static int SetupSystemRegs(int *opmode);
  73. static void bfin_EMAC_setup_addr(bd_t *bd);
  74. #endif