efikamx-usb.c 5.6 KB

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  1. /*
  2. * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  3. *
  4. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <usb.h>
  26. #include <asm/io.h>
  27. #include <asm/arch/imx-regs.h>
  28. #include <asm/arch/mx5x_pins.h>
  29. #include <asm/arch/iomux.h>
  30. #include <asm/gpio.h>
  31. #include <usb/ehci-fsl.h>
  32. #include <usb/ulpi.h>
  33. #include <errno.h>
  34. #include "../../drivers/usb/host/ehci.h"
  35. /* USB pin configuration */
  36. #define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
  37. PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
  38. PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
  39. /*
  40. * Configure the USB H1 and USB H2 IOMUX
  41. */
  42. void setup_iomux_usb(void)
  43. {
  44. setup_iomux_usb_h1();
  45. if (machine_is_efikasb())
  46. setup_iomux_usb_h2();
  47. /* USB PHY reset */
  48. mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
  49. mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
  50. PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
  51. /* USB HUB reset */
  52. mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
  53. mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
  54. PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
  55. /* WIFI EN (act low) */
  56. mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
  57. mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
  58. /* WIFI RESET */
  59. mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
  60. mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
  61. /* BT EN (act low) */
  62. mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
  63. mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
  64. }
  65. /*
  66. * Enable devices connected to USB BUSes
  67. */
  68. static void efika_usb_enable_devices(void)
  69. {
  70. /* Enable Bluetooth */
  71. gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
  72. udelay(10000);
  73. gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
  74. /* Enable WiFi */
  75. gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
  76. udelay(10000);
  77. /* Reset the WiFi chip */
  78. gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
  79. udelay(10000);
  80. gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
  81. }
  82. /*
  83. * Reset USB HUB (or HUBs on EfikaSB)
  84. */
  85. static void efika_usb_hub_reset(void)
  86. {
  87. /* HUB reset */
  88. gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
  89. udelay(1000);
  90. gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
  91. udelay(1000);
  92. gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
  93. }
  94. /*
  95. * Reset USB PHY (or PHYs on EfikaSB)
  96. */
  97. static void efika_usb_phy_reset(void)
  98. {
  99. /* SMSC 3317 PHY reset */
  100. gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
  101. udelay(1000);
  102. gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
  103. }
  104. static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio,
  105. uint32_t alt0, uint32_t alt1)
  106. {
  107. int ret;
  108. struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
  109. struct ulpi_viewport ulpi_vp;
  110. mxc_request_iomux(stp_gpio, alt0);
  111. mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH |
  112. PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
  113. gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0);
  114. udelay(1000);
  115. gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1);
  116. udelay(1000);
  117. mxc_request_iomux(stp_gpio, alt1);
  118. mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG);
  119. udelay(10000);
  120. ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
  121. ulpi_vp.port_num = 0;
  122. ret = ulpi_init(&ulpi_vp);
  123. if (ret) {
  124. printf("Efika USB ULPI initialization failed\n");
  125. return;
  126. }
  127. /* ULPI set flags */
  128. ulpi_write(&ulpi_vp, &ulpi->otg_ctrl,
  129. ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN |
  130. ULPI_OTG_EXTVBUSIND);
  131. ulpi_write(&ulpi_vp, &ulpi->function_ctrl,
  132. ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL |
  133. ULPI_FC_SUSPENDM);
  134. ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0);
  135. /* Set VBus */
  136. ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set,
  137. ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
  138. /*
  139. * Set VBusChrg
  140. *
  141. * NOTE: This violates USB specification, but otherwise, USB on Efika
  142. * doesn't work.
  143. */
  144. ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
  145. }
  146. int board_ehci_hcd_init(int port)
  147. {
  148. /* Init iMX51 EHCI */
  149. efika_usb_phy_reset();
  150. efika_usb_hub_reset();
  151. efika_usb_enable_devices();
  152. return 0;
  153. }
  154. void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
  155. {
  156. uint32_t port = OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT);
  157. struct usb_ehci *ehci = (struct usb_ehci *)port;
  158. struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
  159. struct ulpi_viewport ulpi_vp;
  160. ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
  161. ulpi_vp.port_num = 0;
  162. ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS);
  163. mdelay(50);
  164. /* terminate the reset */
  165. *reg = ehci_readl(status_reg);
  166. *reg |= EHCI_PS_PE;
  167. }
  168. void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
  169. {
  170. uint32_t tmp;
  171. if (port == 0) {
  172. /* Adjust UTMI PHY frequency to 24MHz */
  173. tmp = readl(OTG_BASE_ADDR + 0x80c);
  174. tmp = (tmp & ~0x3) | 0x01;
  175. writel(tmp, OTG_BASE_ADDR + 0x80c);
  176. } else if (port == 1) {
  177. efika_ehci_init(ehci, MX51_PIN_USBH1_STP,
  178. IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0);
  179. } else if ((port == 2) && machine_is_efikasb()) {
  180. efika_ehci_init(ehci, MX51_PIN_EIM_A26,
  181. IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2);
  182. }
  183. if (port)
  184. mdelay(10);
  185. }