lowlevel_init.S 2.3 KB

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  1. /*
  2. * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  3. *
  4. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  5. *
  6. * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <config.h>
  24. #include <asm-offsets.h>
  25. #include <asm/arch/imx-regs.h>
  26. #include <generated/asm-offsets.h>
  27. /*
  28. * Configuration for the flea3 board.
  29. * These defines are used by the included macros and must
  30. * be defined first
  31. */
  32. #define AIPS_MPR_CONFIG 0x77777777
  33. #define AIPS_OPACR_CONFIG 0x00000000
  34. /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
  35. #define MAX_MPR_CONFIG 0x00302154
  36. /* SGPCR - always park on last master */
  37. #define MAX_SGPCR_CONFIG 0x00000010
  38. /* MGPCR - restore default values */
  39. #define MAX_MGPCR_CONFIG 0x00000000
  40. /*
  41. * M3IF Control Register (M3IFCTL)
  42. * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
  43. * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
  44. * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
  45. * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
  46. * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
  47. * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
  48. * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
  49. * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
  50. * ------------
  51. * 0x00000040
  52. */
  53. #define M3IF_CONFIG 0x00000040
  54. #define CCM_PDR0_CONFIG 0x00801000
  55. /*
  56. * includes MX35 utility macros
  57. */
  58. #include <asm/arch/lowlevel_macro.S>
  59. .globl lowlevel_init
  60. lowlevel_init:
  61. core_init
  62. init_aips
  63. init_max
  64. init_m3if
  65. mov pc, lr