start.S 6.8 KB

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  1. /*
  2. * armboot - Startup Code for ARM720 CPU-core
  3. *
  4. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  5. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include "config.h"
  26. #include "version.h"
  27. /*
  28. *************************************************************************
  29. *
  30. * Jump vector table as in table 3.1 in [1]
  31. *
  32. *************************************************************************
  33. */
  34. .globl _start
  35. _start: b reset
  36. ldr pc, _undefined_instruction
  37. ldr pc, _software_interrupt
  38. ldr pc, _prefetch_abort
  39. ldr pc, _data_abort
  40. ldr pc, _not_used
  41. ldr pc, _irq
  42. ldr pc, _fiq
  43. _undefined_instruction: .word undefined_instruction
  44. _software_interrupt: .word software_interrupt
  45. _prefetch_abort: .word prefetch_abort
  46. _data_abort: .word data_abort
  47. _not_used: .word not_used
  48. _irq: .word irq
  49. _fiq: .word fiq
  50. .balignl 16,0xdeadbeef
  51. /*
  52. *************************************************************************
  53. *
  54. * Startup Code (reset vector)
  55. *
  56. * do important init only if we don't start from memory!
  57. * relocate armboot to ram
  58. * setup stack
  59. * jump to second stage
  60. *
  61. *************************************************************************
  62. */
  63. _TEXT_BASE:
  64. .word TEXT_BASE
  65. .globl _armboot_start
  66. _armboot_start:
  67. .word _start
  68. /*
  69. * Note: _armboot_end_data and _armboot_end are defined
  70. * by the (board-dependent) linker script.
  71. * _armboot_end_data is the first usable FLASH address after armboot
  72. */
  73. .globl _armboot_end_data
  74. _armboot_end_data:
  75. .word armboot_end_data
  76. /*
  77. * Note: armboot_end is defined by the (board-dependent) linker script
  78. */
  79. .globl _armboot_end
  80. _armboot_end:
  81. .word armboot_end
  82. #ifdef CONFIG_USE_IRQ
  83. /* IRQ stack memory (calculated at run-time) */
  84. .globl IRQ_STACK_START
  85. IRQ_STACK_START:
  86. .word 0x0badc0de
  87. /* IRQ stack memory (calculated at run-time) */
  88. .globl FIQ_STACK_START
  89. FIQ_STACK_START:
  90. .word 0x0badc0de
  91. #endif
  92. /*
  93. * the actual reset code
  94. */
  95. reset:
  96. /*
  97. * set the cpu to SVC32 mode
  98. */
  99. mrs r0,cpsr
  100. bic r0,r0,#0x1f
  101. orr r0,r0,#0x13
  102. msr cpsr,r0
  103. /*
  104. * relocate exeception table
  105. */
  106. ldr r0, =_start
  107. ldr r1, =0x0
  108. mov r2, #16
  109. copyex:
  110. subs r2, r2, #1
  111. ldr r3, [r0], #4
  112. str r3, [r1], #4
  113. bne copyex
  114. /*
  115. * we do sys-critical inits only at reboot,
  116. * not when booting from ram!
  117. */
  118. #ifdef CONFIG_INIT_CRITICAL
  119. bl cpu_init_crit
  120. #endif
  121. /* Set up the stack */
  122. stack_setup:
  123. ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
  124. sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
  125. sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
  126. #ifdef CONFIG_USE_IRQ
  127. sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
  128. #endif
  129. sub sp, r0, #12 /* leave 3 words for abort-stack */
  130. ldr pc,_start_armboot
  131. _start_armboot: .word start_armboot
  132. /*
  133. *************************************************************************
  134. *
  135. * CPU_init_critical registers
  136. *
  137. *************************************************************************
  138. */
  139. cpu_init_crit:
  140. # actually do nothing for now!
  141. mov pc, lr
  142. /*
  143. *************************************************************************
  144. *
  145. * Interrupt handling
  146. *
  147. *************************************************************************
  148. */
  149. @
  150. @ IRQ stack frame.
  151. @
  152. #define S_FRAME_SIZE 72
  153. #define S_OLD_R0 68
  154. #define S_PSR 64
  155. #define S_PC 60
  156. #define S_LR 56
  157. #define S_SP 52
  158. #define S_IP 48
  159. #define S_FP 44
  160. #define S_R10 40
  161. #define S_R9 36
  162. #define S_R8 32
  163. #define S_R7 28
  164. #define S_R6 24
  165. #define S_R5 20
  166. #define S_R4 16
  167. #define S_R3 12
  168. #define S_R2 8
  169. #define S_R1 4
  170. #define S_R0 0
  171. #define MODE_SVC 0x13
  172. #define I_BIT 0x80
  173. /*
  174. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  175. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  176. */
  177. .macro bad_save_user_regs
  178. sub sp, sp, #S_FRAME_SIZE
  179. stmia sp, {r0 - r12} @ Calling r0-r12
  180. add r8, sp, #S_PC
  181. ldr r2, _armboot_end
  182. add r2, r2, #CONFIG_STACKSIZE
  183. sub r2, r2, #8
  184. ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
  185. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  186. add r5, sp, #S_SP
  187. mov r1, lr
  188. stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
  189. mov r0, sp
  190. .endm
  191. .macro irq_save_user_regs
  192. sub sp, sp, #S_FRAME_SIZE
  193. stmia sp, {r0 - r12} @ Calling r0-r12
  194. add r8, sp, #S_PC
  195. stmdb r8, {sp, lr}^ @ Calling SP, LR
  196. str lr, [r8, #0] @ Save calling PC
  197. mrs r6, spsr
  198. str r6, [r8, #4] @ Save CPSR
  199. str r0, [r8, #8] @ Save OLD_R0
  200. mov r0, sp
  201. .endm
  202. .macro irq_restore_user_regs
  203. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  204. mov r0, r0
  205. ldr lr, [sp, #S_PC] @ Get PC
  206. add sp, sp, #S_FRAME_SIZE
  207. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  208. .endm
  209. .macro get_bad_stack
  210. ldr r13, _armboot_end @ setup our mode stack
  211. add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
  212. sub r13, r13, #8
  213. str lr, [r13] @ save caller lr / spsr
  214. mrs lr, spsr
  215. str lr, [r13, #4]
  216. mov r13, #MODE_SVC @ prepare SVC-Mode
  217. msr spsr_c, r13
  218. mov lr, pc
  219. movs pc, lr
  220. .endm
  221. .macro get_irq_stack @ setup IRQ stack
  222. ldr sp, IRQ_STACK_START
  223. .endm
  224. .macro get_fiq_stack @ setup FIQ stack
  225. ldr sp, FIQ_STACK_START
  226. .endm
  227. /*
  228. * exception handlers
  229. */
  230. .align 5
  231. undefined_instruction:
  232. get_bad_stack
  233. bad_save_user_regs
  234. bl do_undefined_instruction
  235. .align 5
  236. software_interrupt:
  237. get_bad_stack
  238. bad_save_user_regs
  239. bl do_software_interrupt
  240. .align 5
  241. prefetch_abort:
  242. get_bad_stack
  243. bad_save_user_regs
  244. bl do_prefetch_abort
  245. .align 5
  246. data_abort:
  247. get_bad_stack
  248. bad_save_user_regs
  249. bl do_data_abort
  250. .align 5
  251. not_used:
  252. get_bad_stack
  253. bad_save_user_regs
  254. bl do_not_used
  255. #ifdef CONFIG_USE_IRQ
  256. .align 5
  257. irq:
  258. get_irq_stack
  259. irq_save_user_regs
  260. bl do_irq
  261. irq_restore_user_regs
  262. .align 5
  263. fiq:
  264. get_fiq_stack
  265. /* someone ought to write a more effiction fiq_save_user_regs */
  266. irq_save_user_regs
  267. bl do_fiq
  268. irq_restore_user_regs
  269. #else
  270. .align 5
  271. irq:
  272. get_bad_stack
  273. bad_save_user_regs
  274. bl do_irq
  275. .align 5
  276. fiq:
  277. get_bad_stack
  278. bad_save_user_regs
  279. bl do_fiq
  280. #endif
  281. .align 5
  282. .globl reset_cpu
  283. reset_cpu:
  284. mov pc, r0