uboot-vybrid_public/arch/arm/include/asm/arch-vf610/vf610_qspi.h

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __DRIVERS_SPI_VF600QSPI_H__
#define __DRIVERS_SPI_VF600QSPI_H__

#define __swap_16(x) \
		({ unsigned short x_ = (unsigned short)x; \
		(unsigned short)( \
			((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \
	       })
#define __swap_32(x) \
		({ unsigned long x_ = (unsigned long)x; \
		(unsigned long)( \
			((x_ & 0x000000FFUL) << 24) | \
			((x_ & 0x0000FF00UL) <<  8) | \
			((x_ & 0x00FF0000UL) >>  8) | \
			((x_ & 0xFF000000UL) >> 24)); \
		})


#define QSPI_ARDB (*(volatile unsigned int *) 0x7C000000)

/* Lookup Table Instructions */
#define STOP		0
#define CMD		1
#define ADDR		2
#define DUMMY		3
#define MODE		4
#define MODE2		5
#define MODE4		6
#define READ		7
#define WRITE		8
#define JMP_ON_CS	9
#define ADDR_DDR	10
#define MODE_DDR	11
#define MODE2_DDR	12
#define MODE4_DDR	13
#define READ_DDR	14
#define WRITE_DDR	15
#define DATA_LEARN	16

#define QSPI_FLASH_PGSZ			0x100
#define QSPI0_FLASH_BASE_ADDR		0x20000000
#define QSPI1_FLASH_BASE_ADDR		0x50000000

#ifndef QSPI0_TOP_FLASH_A1_ADDR
#define QSPI0_TOP_FLASH_A1_ADDR		0x21000000
#endif
#ifndef QSPI0_TOP_FLASH_B1_ADDR
#define QSPI0_TOP_FLASH_B1_ADDR		0x22000000
#endif

#ifndef QSPI1_TOP_FLASH_A1_ADDR
#define QSPI1_TOP_FLASH_A1_ADDR		0x51000000
#endif
#ifndef QSPI1_TOP_FLASH_B1_ADDR
#define QSPI1_TOP_FLASH_B1_ADDR		0x52000000
#endif

/* QuadSPI LUT Bit Fields */
#define QuadSPI_LUT_OPRND0_MASK		0xFFu
#define QuadSPI_LUT_OPRND0_SHIFT	0
#define QuadSPI_LUT_OPRND0(x)		((u32)(((u32)(x))<<QuadSPI_LUT_OPRND0_SHIFT))
#define QuadSPI_LUT_PAD0_MASK		0x300u
#define QuadSPI_LUT_PAD0_SHIFT		8
#define QuadSPI_LUT_PAD0(x)             ((u32)(((u32)(x))<<QuadSPI_LUT_PAD0_SHIFT))
#define QuadSPI_LUT_INSTR0_MASK		0xFC00u
#define QuadSPI_LUT_INSTR0_SHIFT	10
#define QuadSPI_LUT_INSTR0(x)		((u32)(((u32)(x))<<QuadSPI_LUT_INSTR0_SHIFT))
#define QuadSPI_LUT_OPRND1_MASK		0xFF0000u
#define QuadSPI_LUT_OPRND1_SHIFT	16
#define QuadSPI_LUT_OPRND1(x)		((u32)(((u32)(x))<<QuadSPI_LUT_OPRND1_SHIFT))
#define QuadSPI_LUT_PAD1_MASK		0x3000000u
#define QuadSPI_LUT_PAD1_SHIFT		24
#define QuadSPI_LUT_PAD1(x)		((u32)(((u32)(x))<<QuadSPI_LUT_PAD1_SHIFT))
#define QuadSPI_LUT_INSTR1_MASK		0xFC000000u
#define QuadSPI_LUT_INSTR1_SHIFT	26
#define QuadSPI_LUT_INSTR1(x)		((u32)(((u32)(x))<<QuadSPI_LUT_INSTR1_SHIFT))

#endif