dsp.c 1.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970
  1. /*
  2. * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
  3. *
  4. * Developed for DENX Software Engineering GmbH
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <post.h>
  26. #if CONFIG_POST & CONFIG_SYS_POST_DSP
  27. #include <asm/io.h>
  28. /* This test verifies DSP status bits in FPGA */
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define DSP_STATUS_REG 0xC4000008
  31. #define FPGA_STATUS_REG 0xC400000C
  32. int dsp_post_test(int flags)
  33. {
  34. uint old_value;
  35. uint read_value;
  36. int ret;
  37. /* momorize fpga status */
  38. old_value = in_be32((void *)FPGA_STATUS_REG);
  39. /* enable outputs */
  40. out_be32((void *)FPGA_STATUS_REG, 0x30);
  41. /* generate sync signal */
  42. out_be32((void *)DSP_STATUS_REG, 0x300);
  43. udelay(5);
  44. out_be32((void *)DSP_STATUS_REG, 0);
  45. udelay(500);
  46. /* read status */
  47. ret = 0;
  48. read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
  49. if (read_value != 0x03) {
  50. post_log("\nDSP status read %08X\n", read_value);
  51. ret = 1;
  52. }
  53. /* restore fpga status */
  54. out_be32((void *)FPGA_STATUS_REG, old_value);
  55. return ret;
  56. }
  57. #endif /* CONFIG_POST & CONFIG_SYS_POST_DSP */