fsl_pmic.h 2.7 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4. *
  5. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #ifndef __FSL_PMIC_H__
  26. #define __FSL_PMIC_H__
  27. /*
  28. * The registers of different PMIC has the same meaning
  29. * but the bit positions of the fields can differ or
  30. * some fields has a meaning only on some devices.
  31. * You have to check with the internal SPI bitmap
  32. * (see Freescale Documentation) to set the registers
  33. * for the device you are using
  34. */
  35. enum {
  36. REG_INT_STATUS0 = 0,
  37. REG_INT_MASK0,
  38. REG_INT_SENSE0,
  39. REG_INT_STATUS1,
  40. REG_INT_MASK1,
  41. REG_INT_SENSE1,
  42. REG_PU_MODE_S,
  43. REG_IDENTIFICATION,
  44. REG_UNUSED0,
  45. REG_ACC0,
  46. REG_ACC1, /*10 */
  47. REG_UNUSED1,
  48. REG_UNUSED2,
  49. REG_POWER_CTL0,
  50. REG_POWER_CTL1,
  51. REG_POWER_CTL2,
  52. REG_REGEN_ASSIGN,
  53. REG_UNUSED3,
  54. REG_MEM_A,
  55. REG_MEM_B,
  56. REG_RTC_TIME, /*20 */
  57. REG_RTC_ALARM,
  58. REG_RTC_DAY,
  59. REG_RTC_DAY_ALARM,
  60. REG_SW_0,
  61. REG_SW_1,
  62. REG_SW_2,
  63. REG_SW_3,
  64. REG_SW_4,
  65. REG_SW_5,
  66. REG_SETTING_0, /*30 */
  67. REG_SETTING_1,
  68. REG_MODE_0,
  69. REG_MODE_1,
  70. REG_POWER_MISC,
  71. REG_UNUSED4,
  72. REG_UNUSED5,
  73. REG_UNUSED6,
  74. REG_UNUSED7,
  75. REG_UNUSED8,
  76. REG_UNUSED9, /*40 */
  77. REG_UNUSED10,
  78. REG_UNUSED11,
  79. REG_ADC0,
  80. REG_ADC1,
  81. REG_ADC2,
  82. REG_ADC3,
  83. REG_ADC4,
  84. REG_CHARGE,
  85. REG_USB0,
  86. REG_USB1, /*50 */
  87. REG_LED_CTL0,
  88. REG_LED_CTL1,
  89. REG_LED_CTL2,
  90. REG_LED_CTL3,
  91. REG_UNUSED12,
  92. REG_UNUSED13,
  93. REG_TRIM0,
  94. REG_TRIM1,
  95. REG_TEST0,
  96. REG_TEST1, /*60 */
  97. REG_TEST2,
  98. REG_TEST3,
  99. REG_TEST4,
  100. };
  101. /* REG_POWER_MISC */
  102. #define GPO1EN (1 << 6)
  103. #define GPO1STBY (1 << 7)
  104. #define GPO2EN (1 << 8)
  105. #define GPO2STBY (1 << 9)
  106. #define GPO3EN (1 << 10)
  107. #define GPO3STBY (1 << 11)
  108. #define GPO4EN (1 << 12)
  109. #define GPO4STBY (1 << 13)
  110. #define PWGT1SPIEN (1 << 15)
  111. #define PWGT2SPIEN (1 << 16)
  112. #define PWUP (1 << 21)
  113. /* Power Control 0 */
  114. #define COINCHEN (1 << 23)
  115. #define BATTDETEN (1 << 19)
  116. /* Interrupt status 1 */
  117. #define RTCRSTI (1 << 7)
  118. void pmic_show_pmic_info(void);
  119. void pmic_reg_write(u32 reg, u32 value);
  120. u32 pmic_reg_read(u32 reg);
  121. #endif