bluestone.h 6.0 KB

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  1. /*
  2. * bluestone.h - configuration for Bluestone (APM821XX)
  3. *
  4. * Copyright (c) 2010, Applied Micro Circuits Corporation
  5. * Author: Tirumala R Marri <tmarri@apm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef __CONFIG_H
  23. #define __CONFIG_H
  24. /*
  25. * High Level Configuration Options
  26. */
  27. #define CONFIG_APM821XX 1 /* APM821XX series */
  28. #define CONFIG_HOSTNAME bluestone
  29. #define CONFIG_4xx 1 /* ... PPC4xx family */
  30. #define CONFIG_440 1
  31. #ifndef CONFIG_SYS_TEXT_BASE
  32. #define CONFIG_SYS_TEXT_BASE 0xFFFA0000
  33. #endif
  34. /*
  35. * Include common defines/options for all AMCC eval boards
  36. */
  37. #include "amcc-common.h"
  38. #define CONFIG_SYS_CLK_FREQ 50000000
  39. #define CONFIG_BOARD_TYPES 1 /* support board types */
  40. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  41. #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
  42. /*
  43. * Base addresses -- Note these are effective addresses where the
  44. * actual resources get mapped (not physical addresses)
  45. */
  46. /* EBC stuff */
  47. /* later mapped to this addr */
  48. #define CONFIG_SYS_FLASH_BASE 0xFFF00000
  49. #define CONFIG_SYS_FLASH_SIZE (4 << 20) /* 1MB usable */
  50. /* EBC Boot Space: 0xFF000000 */
  51. #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000
  52. #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 32k */
  53. #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
  54. #define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals*/
  55. #define CONFIG_SYS_SRAM_SIZE (256 << 10)
  56. /*
  57. * Initial RAM & stack pointer (placed in OCM)
  58. */
  59. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
  60. #define CONFIG_SYS_INIT_RAM_END (4 << 10)
  61. #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
  62. #define CONFIG_SYS_GBL_DATA_OFFSET \
  63. (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  64. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  65. /*
  66. * Environment
  67. */
  68. /*
  69. * Define here the location of the environment variables (FLASH).
  70. */
  71. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  72. /*
  73. * FLASH related
  74. */
  75. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  76. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  77. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
  78. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  79. /* max number of memory banks */
  80. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  81. /* max number of sectors on one chip */
  82. #define CONFIG_SYS_MAX_FLASH_SECT 80
  83. /* Timeout for Flash Erase (in ms) */
  84. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000
  85. /* Timeout for Flash Write (in ms) */
  86. #define CONFIG_SYS_FLASH_WRITE_TOUT 500
  87. /* use buffered writes (20x faster) */
  88. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  89. /* print 'E' for empty sector on flinfo */
  90. #define CONFIG_SYS_FLASH_EMPTY_INFO
  91. #ifdef CONFIG_ENV_IS_IN_FLASH
  92. #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
  93. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  94. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  95. /* Address and size of Redundant Environment Sector */
  96. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
  97. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  98. #endif /* CONFIG_ENV_IS_IN_FLASH */
  99. /* SDRAM */
  100. #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
  101. #define SPD_EEPROM_ADDRESS {0x53, 0x51} /* SPD i2c spd addresses */
  102. #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
  103. #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
  104. #define CONFIG_DDR_ECC 1 /* with ECC support */
  105. /*
  106. * Serial Port
  107. */
  108. #define CONFIG_CONS_INDEX 1 /* Use UART0 */
  109. /*
  110. * I2C
  111. */
  112. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
  113. #define CONFIG_SYS_I2C_MULTI_EEPROMS
  114. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
  115. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  116. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  117. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* Data sheet */
  118. /* I2C bootstrap EEPROM */
  119. #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
  120. #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
  121. #define CONFIG_4xx_CONFIG_BLOCKSIZE 16
  122. /*
  123. * Ethernet
  124. */
  125. #define CONFIG_IBM_EMAC4_V4 1
  126. #define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_NONE_RGMII
  127. #define CONFIG_HAS_ETH0
  128. /* PHY address, See schematics */
  129. #define CONFIG_PHY_ADDR 0x1f
  130. /* reset phy upon startup */
  131. #define CONFIG_PHY_RESET 1
  132. /* Include GbE speed/duplex detection */
  133. #define CONFIG_PHY_GIGE 1
  134. #define CONFIG_PHY_DYNAMIC_ANEG 1
  135. /*
  136. * External Bus Controller (EBC) Setup
  137. **/
  138. #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_LOCK | \
  139. EBC_CFG_PTD_ENABLE | \
  140. EBC_CFG_RTC_2048PERCLK | \
  141. EBC_CFG_ATC_HI | \
  142. EBC_CFG_DTC_HI | \
  143. EBC_CFG_CTC_HI | \
  144. EBC_CFG_OEO_PREVIOUS)
  145. /* NOR Flash */
  146. #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
  147. EBC_BXAP_TWT_ENCODE(64) | \
  148. EBC_BXAP_BCE_DISABLE | \
  149. EBC_BXAP_BCT_2TRANS | \
  150. EBC_BXAP_CSN_ENCODE(1) | \
  151. EBC_BXAP_OEN_ENCODE(2) | \
  152. EBC_BXAP_WBN_ENCODE(2) | \
  153. EBC_BXAP_WBF_ENCODE(2) | \
  154. EBC_BXAP_TH_ENCODE(7) | \
  155. EBC_BXAP_SOR_DELAYED | \
  156. EBC_BXAP_BEM_WRITEONLY | \
  157. EBC_BXAP_PEN_DISABLED)
  158. /* Peripheral Bank Configuration Register - EBC_BxCR */
  159. #define CONFIG_SYS_EBC_PB0CR \
  160. (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
  161. EBC_BXCR_BS_1MB | \
  162. EBC_BXCR_BU_RW | \
  163. EBC_BXCR_BW_8BIT)
  164. #endif /* __CONFIG_H */