NX823.h 13 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  4. *
  5. * (C) Copyright 2001
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * board/config.h - configuration options, board specific
  28. */
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. /*
  32. * High Level Configuration Options
  33. * (easy to change)
  34. */
  35. #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
  36. #define CONFIG_NX823 1 /* ...on a NEXUS 823 module */
  37. #define CONFIG_SYS_TEXT_BASE 0x40000000
  38. /*#define CONFIG_VIDEO 1 */
  39. #define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
  40. #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  41. #undef CONFIG_8xx_CONS_SMC2
  42. #undef CONFIG_8xx_CONS_NONE
  43. #define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */
  44. #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
  45. #define CONFIG_BOOTARGS "ramdisk_size=8000 "\
  46. "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\
  47. "nfsaddrs=10.77.77.20:10.77.77.250"
  48. #define CONFIG_BOOTCOMMAND "bootm 400e0000"
  49. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  50. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  51. #undef CONFIG_WATCHDOG /* watchdog disabled, for now */
  52. #define CONFIG_SOURCE
  53. /*
  54. * BOOTP options
  55. */
  56. #define CONFIG_BOOTP_SUBNETMASK
  57. #define CONFIG_BOOTP_GATEWAY
  58. #define CONFIG_BOOTP_HOSTNAME
  59. #define CONFIG_BOOTP_BOOTPATH
  60. #define CONFIG_BOOTP_BOOTFILESIZE
  61. /*
  62. * Command line configuration.
  63. */
  64. #include <config_cmd_default.h>
  65. #define CONFIG_CMD_SOURCE
  66. /* call various generic functions */
  67. #define CONFIG_MISC_INIT_R
  68. /*
  69. * Miscellaneous configurable options
  70. */
  71. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  72. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  73. #if defined(CONFIG_CMD_KGDB)
  74. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  75. #else
  76. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  77. #endif
  78. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  79. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  80. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  81. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  82. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  83. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  84. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  85. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  86. /*
  87. * Low Level Configuration Settings
  88. * (address mappings, register initial values, etc.)
  89. * You should know what you are doing if you make changes here.
  90. */
  91. /*-----------------------------------------------------------------------
  92. * Internal Memory Mapped Register
  93. */
  94. #define CONFIG_SYS_IMMR 0xFFF00000
  95. /*-----------------------------------------------------------------------
  96. * Definitions for initial stack pointer and data area (in DPRAM)
  97. */
  98. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  99. #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  100. #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  101. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  102. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  103. /*-----------------------------------------------------------------------
  104. * Start addresses for the final memory configuration
  105. * (Set up by the startup code)
  106. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  107. */
  108. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  109. #define CONFIG_SYS_FLASH_BASE 0x40000000
  110. #define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
  111. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  112. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  113. /*
  114. * For booting Linux, the board info and command line data
  115. * have to be in the first 8 MB of memory, since this is
  116. * the maximum mapped by the Linux kernel during initialization.
  117. */
  118. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  119. /*-----------------------------------------------------------------------
  120. * FLASH organization
  121. */
  122. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  123. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
  124. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  125. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  126. #define CONFIG_ENV_IS_IN_FLASH 1
  127. #define xEMBED
  128. #ifdef EMBED
  129. #define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */
  130. #define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE
  131. #else
  132. #define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */
  133. #define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */
  134. #endif
  135. #define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */
  136. #define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */
  137. #define CONFIG_SYS_FLASH_SN_BYTES 8
  138. /*-----------------------------------------------------------------------
  139. * Cache Configuration
  140. */
  141. #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  142. #if defined(CONFIG_CMD_KGDB)
  143. #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  144. #endif
  145. /*-----------------------------------------------------------------------
  146. * SYPCR - System Protection Control 11-9
  147. * SYPCR can only be written once after reset!
  148. *-----------------------------------------------------------------------
  149. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  150. */
  151. #if defined(CONFIG_WATCHDOG)
  152. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  153. SYPCR_SWE | SYPCR_SWP)
  154. #else
  155. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  156. #endif
  157. /*-----------------------------------------------------------------------
  158. * SIUMCR - SIU Module Configuration 12-30
  159. *-----------------------------------------------------------------------
  160. * PCMCIA config., multi-function pin tri-state
  161. */
  162. #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00)
  163. /*-----------------------------------------------------------------------
  164. * TBSCR - Time Base Status and Control 12-16
  165. *-----------------------------------------------------------------------
  166. * Clear Reference Interrupt Status, Timebase freezing enabled
  167. */
  168. #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  169. /*-----------------------------------------------------------------------
  170. * RTCSC - Real-Time Clock Status and Control Register 12-18
  171. *-----------------------------------------------------------------------
  172. */
  173. #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  174. /*-----------------------------------------------------------------------
  175. * PISCR - Periodic Interrupt Status and Control 12-23
  176. *-----------------------------------------------------------------------
  177. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  178. */
  179. #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
  180. /*-----------------------------------------------------------------------
  181. * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7
  182. *-----------------------------------------------------------------------
  183. * Reset PLL lock status sticky bit, timer expired status bit and timer
  184. * interrupt status bit
  185. */
  186. #define MPC8XX_SPEED 66666666L
  187. #define MPC8XX_XIN 32768 /* 32.768 kHz crystal */
  188. #define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
  189. #define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT)
  190. #define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST)
  191. /*-----------------------------------------------------------------------
  192. * SCCR - System Clock and reset Control Register 5-3
  193. *-----------------------------------------------------------------------
  194. * Set clock output, timebase and RTC source and divider,
  195. * power management and some other internal clocks
  196. */
  197. #define SCCR_MASK SCCR_EBDF11
  198. #define CONFIG_SYS_SCCR (SCCR_TBS | \
  199. SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
  200. SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
  201. SCCR_DFALCD00)
  202. /*-----------------------------------------------------------------------
  203. *
  204. *-----------------------------------------------------------------------
  205. *
  206. */
  207. #define CONFIG_SYS_DER 0
  208. /*
  209. * Init Memory Controller:
  210. *
  211. * BR0 and OR0 (FLASH)
  212. */
  213. #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  214. /* used to re-map FLASH both when starting from SRAM or FLASH:
  215. * restrict access enough to keep SRAM working (if any)
  216. * but not too much to meddle with FLASH accesses
  217. */
  218. #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
  219. #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
  220. /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
  221. #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
  222. OR_SCY_8_CLK )
  223. #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  224. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  225. #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
  226. /*
  227. * BR1/2 and OR1/2 (SDRAM)
  228. */
  229. #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
  230. #define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */
  231. #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
  232. /* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */
  233. #define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM)
  234. #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
  235. #define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  236. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM
  237. #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  238. /* IO and memory mapped stuff */
  239. #define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */
  240. #define NX823_IO_BASE 0xFF000000 /* start of IO */
  241. #define GPOUT_OFFSET (3<<16)
  242. #define QUART_OFFSET (4<<16)
  243. #define VIDAC_OFFSET (5<<16)
  244. #define CPLD_OFFSET (6<<16)
  245. #define SED1386_OFFSET (7<<16)
  246. /*
  247. * BR3 and OR3 (general purpose output latches)
  248. */
  249. #define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET)
  250. #define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI)
  251. #define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING)
  252. #define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V)
  253. /*
  254. * BR4 and OR4 (QUART)
  255. */
  256. #define QUART_BASE (NX823_IO_BASE + QUART_OFFSET)
  257. #define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX)
  258. #define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI)
  259. #define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V)
  260. /*
  261. * BR5 and OR5 (Video DAC)
  262. */
  263. #define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET)
  264. #define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
  265. #define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI)
  266. #define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V)
  267. /*
  268. * BR6 and OR6 (CPLD)
  269. * FIXME timing not verified for CPLD
  270. */
  271. #define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET)
  272. #define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR)
  273. #define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI)
  274. #define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V )
  275. /*
  276. * BR7 and OR7 (SED1386)
  277. * FIXME timing not verified for SED controller
  278. */
  279. #define SED1386_BASE 0xF7000000
  280. #define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA)
  281. #define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V )
  282. /*
  283. * Memory Periodic Timer Prescaler
  284. */
  285. /* periodic timer for refresh */
  286. #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
  287. /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
  288. #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  289. #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  290. /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  291. #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  292. #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  293. /*
  294. * MAMR settings for SDRAM
  295. */
  296. /* 8 column SDRAM */
  297. #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  298. MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
  299. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  300. /* 9 column SDRAM */
  301. #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
  302. MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
  303. MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
  304. #define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */
  305. #define CONFIG_ETHADDR 00:10:20:30:40:50
  306. #define CONFIG_IPADDR 10.77.77.20
  307. #define CONFIG_SERVERIP 10.77.77.250
  308. #endif /* __CONFIG_H */