MPC8536DS.h 26 KB

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  1. /*
  2. * Copyright 2007-2009,2010 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * mpc8536ds board configuration file
  24. *
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #include "../board/freescale/common/ics307_clk.h"
  29. #ifdef CONFIG_36BIT
  30. #define CONFIG_PHYS_64BIT 1
  31. #endif
  32. #ifdef CONFIG_NAND
  33. #define CONFIG_NAND_U_BOOT 1
  34. #define CONFIG_RAMBOOT_NAND 1
  35. #define CONFIG_SYS_TEXT_BASE 0xf8f82000
  36. #endif
  37. #ifdef CONFIG_SDCARD
  38. #define CONFIG_RAMBOOT_SDCARD 1
  39. #define CONFIG_SYS_TEXT_BASE 0xf8f80000
  40. #endif
  41. #ifdef CONFIG_SPIFLASH
  42. #define CONFIG_RAMBOOT_SPIFLASH 1
  43. #define CONFIG_SYS_TEXT_BASE 0xf8f80000
  44. #endif
  45. #ifndef CONFIG_SYS_TEXT_BASE
  46. #define CONFIG_SYS_TEXT_BASE 0xeff80000
  47. #endif
  48. /* High Level Configuration Options */
  49. #define CONFIG_BOOKE 1 /* BOOKE */
  50. #define CONFIG_E500 1 /* BOOKE e500 family */
  51. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  52. #define CONFIG_MPC8536 1
  53. #define CONFIG_MPC8536DS 1
  54. #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
  55. #define CONFIG_PCI 1 /* Enable PCI/PCIE */
  56. #define CONFIG_PCI1 1 /* Enable PCI controller 1 */
  57. #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
  58. #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
  59. #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
  60. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  61. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  62. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  63. #define CONFIG_SYS_HAS_SERDES /* has SERDES */
  64. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  65. #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
  66. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  67. #define CONFIG_ENV_OVERWRITE
  68. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
  69. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  70. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  71. /*
  72. * These can be toggled for performance analysis, otherwise use default.
  73. */
  74. #define CONFIG_L2_CACHE /* toggle L2 cache */
  75. #define CONFIG_BTB /* toggle branch predition */
  76. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  77. #define CONFIG_ENABLE_36BIT_PHYS 1
  78. #ifdef CONFIG_PHYS_64BIT
  79. #define CONFIG_ADDR_MAP 1
  80. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  81. #endif
  82. #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
  83. #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
  84. #define CONFIG_PANIC_HANG /* do not reset board on panic */
  85. /*
  86. * Config the L2 Cache as L2 SRAM
  87. */
  88. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
  89. #ifdef CONFIG_PHYS_64BIT
  90. #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
  91. #else
  92. #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
  93. #endif
  94. #define CONFIG_SYS_L2_SIZE (512 << 10)
  95. #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
  96. /*
  97. * Base addresses -- Note these are effective addresses where the
  98. * actual resources get mapped (not physical addresses)
  99. */
  100. #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  101. #ifdef CONFIG_PHYS_64BIT
  102. #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
  103. #else
  104. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
  105. #endif
  106. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  107. #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
  108. #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
  109. #else
  110. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  111. #endif
  112. /* DDR Setup */
  113. #define CONFIG_VERY_BIG_RAM
  114. #define CONFIG_FSL_DDR2
  115. #undef CONFIG_FSL_DDR_INTERACTIVE
  116. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  117. #define CONFIG_DDR_SPD
  118. #undef CONFIG_DDR_DLL
  119. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  120. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  121. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  122. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  123. #define CONFIG_NUM_DDR_CONTROLLERS 1
  124. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  125. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  126. /* I2C addresses of SPD EEPROMs */
  127. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  128. #define CONFIG_SYS_SPD_BUS_NUM 1
  129. /* These are used when DDR doesn't use SPD. */
  130. #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
  131. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
  132. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
  133. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  134. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  135. #define CONFIG_SYS_DDR_TIMING_1 0x3935d322
  136. #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
  137. #define CONFIG_SYS_DDR_MODE_1 0x00480432
  138. #define CONFIG_SYS_DDR_MODE_2 0x00000000
  139. #define CONFIG_SYS_DDR_INTERVAL 0x06180100
  140. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  141. #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
  142. #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
  143. #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
  144. #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
  145. #define CONFIG_SYS_DDR_CONTROL2 0x04400010
  146. #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
  147. #define CONFIG_SYS_DDR_ERR_DIS 0x00000000
  148. #define CONFIG_SYS_DDR_SBE 0x00010000
  149. /* Make sure required options are set */
  150. #ifndef CONFIG_SPD_EEPROM
  151. #error ("CONFIG_SPD_EEPROM is required")
  152. #endif
  153. #undef CONFIG_CLOCKS_IN_MHZ
  154. /*
  155. * Memory map -- xxx -this is wrong, needs updating
  156. *
  157. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  158. * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
  159. * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
  160. * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
  161. *
  162. * Localbus cacheable (TBD)
  163. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  164. *
  165. * Localbus non-cacheable
  166. * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
  167. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  168. * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
  169. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  170. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  171. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  172. */
  173. /*
  174. * Local Bus Definitions
  175. */
  176. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  177. #ifdef CONFIG_PHYS_64BIT
  178. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  179. #else
  180. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  181. #endif
  182. #define CONFIG_FLASH_BR_PRELIM \
  183. (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
  184. | BR_PS_16 | BR_V)
  185. #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
  186. #define CONFIG_SYS_BR1_PRELIM \
  187. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  188. | BR_PS_16 | BR_V)
  189. #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
  190. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
  191. CONFIG_SYS_FLASH_BASE_PHYS }
  192. #define CONFIG_SYS_FLASH_QUIET_TEST
  193. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  194. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  195. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  196. #undef CONFIG_SYS_FLASH_CHECKSUM
  197. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  198. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  199. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  200. #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
  201. || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
  202. #define CONFIG_SYS_RAMBOOT
  203. #else
  204. #undef CONFIG_SYS_RAMBOOT
  205. #endif
  206. #define CONFIG_FLASH_CFI_DRIVER
  207. #define CONFIG_SYS_FLASH_CFI
  208. #define CONFIG_SYS_FLASH_EMPTY_INFO
  209. #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
  210. #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  211. #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
  212. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  213. #ifdef CONFIG_PHYS_64BIT
  214. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  215. #else
  216. #define PIXIS_BASE_PHYS PIXIS_BASE
  217. #endif
  218. #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  219. #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
  220. #define PIXIS_ID 0x0 /* Board ID at offset 0 */
  221. #define PIXIS_VER 0x1 /* Board version at offset 1 */
  222. #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
  223. #define PIXIS_CSR 0x3 /* PIXIS General control/status register */
  224. #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
  225. #define PIXIS_PWR 0x5 /* PIXIS Power status register */
  226. #define PIXIS_AUX 0x6 /* Auxiliary 1 register */
  227. #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
  228. #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
  229. #define PIXIS_VCTL 0x10 /* VELA Control Register */
  230. #define PIXIS_VSTAT 0x11 /* VELA Status Register */
  231. #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
  232. #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
  233. #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
  234. #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
  235. #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
  236. #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
  237. #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
  238. #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
  239. #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
  240. #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
  241. #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
  242. #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
  243. #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
  244. #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
  245. #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
  246. #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
  247. #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
  248. #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
  249. #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
  250. #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
  251. #define PIXIS_VWATCH 0x24 /* Watchdog Register */
  252. #define PIXIS_LED 0x25 /* LED Register */
  253. #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
  254. /* old pixis referenced names */
  255. #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
  256. #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
  257. #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
  258. #define CONFIG_SYS_INIT_RAM_LOCK 1
  259. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  260. #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
  261. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  262. #define CONFIG_SYS_GBL_DATA_OFFSET \
  263. (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  264. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  265. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  266. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  267. #ifndef CONFIG_NAND_SPL
  268. #define CONFIG_SYS_NAND_BASE 0xffa00000
  269. #ifdef CONFIG_PHYS_64BIT
  270. #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
  271. #else
  272. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  273. #endif
  274. #else
  275. #define CONFIG_SYS_NAND_BASE 0xfff00000
  276. #ifdef CONFIG_PHYS_64BIT
  277. #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
  278. #else
  279. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  280. #endif
  281. #endif
  282. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
  283. CONFIG_SYS_NAND_BASE + 0x40000, \
  284. CONFIG_SYS_NAND_BASE + 0x80000, \
  285. CONFIG_SYS_NAND_BASE + 0xC0000}
  286. #define CONFIG_SYS_MAX_NAND_DEVICE 4
  287. #define CONFIG_MTD_NAND_VERIFY_WRITE
  288. #define CONFIG_CMD_NAND 1
  289. #define CONFIG_NAND_FSL_ELBC 1
  290. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  291. /* NAND boot: 4K NAND loader config */
  292. #define CONFIG_SYS_NAND_SPL_SIZE 0x1000
  293. #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
  294. #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
  295. #define CONFIG_SYS_NAND_U_BOOT_START \
  296. (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
  297. #define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
  298. #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
  299. #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
  300. /* NAND flash config */
  301. #define CONFIG_NAND_BR_PRELIM \
  302. (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  303. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  304. | BR_PS_8 /* Port Size = 8 bit */ \
  305. | BR_MS_FCM /* MSEL = FCM */ \
  306. | BR_V) /* valid */
  307. #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
  308. | OR_FCM_PGS /* Large Page*/ \
  309. | OR_FCM_CSCT \
  310. | OR_FCM_CST \
  311. | OR_FCM_CHT \
  312. | OR_FCM_SCY_1 \
  313. | OR_FCM_TRLX \
  314. | OR_FCM_EHTR)
  315. #ifdef CONFIG_RAMBOOT_NAND
  316. #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  317. #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  318. #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  319. #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  320. #else
  321. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  322. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  323. #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
  324. #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  325. #endif
  326. #define CONFIG_SYS_BR4_PRELIM \
  327. (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
  328. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  329. | BR_PS_8 /* Port Size = 8 bit */ \
  330. | BR_MS_FCM /* MSEL = FCM */ \
  331. | BR_V) /* valid */
  332. #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  333. #define CONFIG_SYS_BR5_PRELIM \
  334. (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
  335. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  336. | BR_PS_8 /* Port Size = 8 bit */ \
  337. | BR_MS_FCM /* MSEL = FCM */ \
  338. | BR_V) /* valid */
  339. #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  340. #define CONFIG_SYS_BR6_PRELIM \
  341. (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
  342. | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
  343. | BR_PS_8 /* Port Size = 8 bit */ \
  344. | BR_MS_FCM /* MSEL = FCM */ \
  345. | BR_V) /* valid */
  346. #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
  347. /* Serial Port - controlled on board with jumper J8
  348. * open - index 2
  349. * shorted - index 1
  350. */
  351. #define CONFIG_CONS_INDEX 1
  352. #define CONFIG_SYS_NS16550
  353. #define CONFIG_SYS_NS16550_SERIAL
  354. #define CONFIG_SYS_NS16550_REG_SIZE 1
  355. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  356. #ifdef CONFIG_NAND_SPL
  357. #define CONFIG_NS16550_MIN_FUNCTIONS
  358. #endif
  359. #define CONFIG_SYS_BAUDRATE_TABLE \
  360. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  361. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  362. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  363. /* Use the HUSH parser */
  364. #define CONFIG_SYS_HUSH_PARSER
  365. #ifdef CONFIG_SYS_HUSH_PARSER
  366. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  367. #endif
  368. /*
  369. * Pass open firmware flat tree
  370. */
  371. #define CONFIG_OF_LIBFDT 1
  372. #define CONFIG_OF_BOARD_SETUP 1
  373. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  374. /*
  375. * I2C
  376. */
  377. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  378. #define CONFIG_HARD_I2C /* I2C with hardware support */
  379. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  380. #define CONFIG_I2C_MULTI_BUS
  381. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  382. #define CONFIG_SYS_I2C_SLAVE 0x7F
  383. #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */
  384. #define CONFIG_SYS_I2C_OFFSET 0x3000
  385. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  386. /*
  387. * I2C2 EEPROM
  388. */
  389. #define CONFIG_ID_EEPROM
  390. #ifdef CONFIG_ID_EEPROM
  391. #define CONFIG_SYS_I2C_EEPROM_NXID
  392. #endif
  393. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  394. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  395. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  396. /*
  397. * General PCI
  398. * Memory space is mapped 1-1, but I/O space must start from 0.
  399. */
  400. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  401. #ifdef CONFIG_PHYS_64BIT
  402. #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
  403. #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
  404. #else
  405. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  406. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  407. #endif
  408. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  409. #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
  410. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  411. #ifdef CONFIG_PHYS_64BIT
  412. #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
  413. #else
  414. #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
  415. #endif
  416. #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
  417. /* controller 1, Slot 1, tgtid 1, Base address a000 */
  418. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
  419. #ifdef CONFIG_PHYS_64BIT
  420. #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
  421. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
  422. #else
  423. #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
  424. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
  425. #endif
  426. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
  427. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
  428. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  429. #ifdef CONFIG_PHYS_64BIT
  430. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
  431. #else
  432. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
  433. #endif
  434. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  435. /* controller 2, Slot 2, tgtid 2, Base address 9000 */
  436. #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
  437. #ifdef CONFIG_PHYS_64BIT
  438. #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
  439. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
  440. #else
  441. #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
  442. #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
  443. #endif
  444. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
  445. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
  446. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  447. #ifdef CONFIG_PHYS_64BIT
  448. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
  449. #else
  450. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
  451. #endif
  452. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  453. /* controller 3, direct to uli, tgtid 3, Base address 8000 */
  454. #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
  455. #ifdef CONFIG_PHYS_64BIT
  456. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  457. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
  458. #else
  459. #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
  460. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
  461. #endif
  462. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  463. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
  464. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  465. #ifdef CONFIG_PHYS_64BIT
  466. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
  467. #else
  468. #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
  469. #endif
  470. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  471. #if defined(CONFIG_PCI)
  472. #define CONFIG_NET_MULTI
  473. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  474. /*PCIE video card used*/
  475. #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
  476. /*PCI video card used*/
  477. /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
  478. /* video */
  479. #define CONFIG_VIDEO
  480. #if defined(CONFIG_VIDEO)
  481. #define CONFIG_BIOSEMU
  482. #define CONFIG_CFB_CONSOLE
  483. #define CONFIG_VIDEO_SW_CURSOR
  484. #define CONFIG_VGA_AS_SINGLE_DEVICE
  485. #define CONFIG_ATI_RADEON_FB
  486. #define CONFIG_VIDEO_LOGO
  487. /*#define CONFIG_CONSOLE_CURSOR*/
  488. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
  489. #endif
  490. #undef CONFIG_EEPRO100
  491. #undef CONFIG_TULIP
  492. #undef CONFIG_RTL8139
  493. #ifndef CONFIG_PCI_PNP
  494. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
  495. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
  496. #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
  497. #endif
  498. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  499. #endif /* CONFIG_PCI */
  500. /* SATA */
  501. #define CONFIG_LIBATA
  502. #define CONFIG_FSL_SATA
  503. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  504. #define CONFIG_SATA1
  505. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  506. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  507. #define CONFIG_SATA2
  508. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  509. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  510. #ifdef CONFIG_FSL_SATA
  511. #define CONFIG_LBA48
  512. #define CONFIG_CMD_SATA
  513. #define CONFIG_DOS_PARTITION
  514. #define CONFIG_CMD_EXT2
  515. #endif
  516. #if defined(CONFIG_TSEC_ENET)
  517. #ifndef CONFIG_NET_MULTI
  518. #define CONFIG_NET_MULTI 1
  519. #endif
  520. #define CONFIG_MII 1 /* MII PHY management */
  521. #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
  522. #define CONFIG_TSEC1 1
  523. #define CONFIG_TSEC1_NAME "eTSEC1"
  524. #define CONFIG_TSEC3 1
  525. #define CONFIG_TSEC3_NAME "eTSEC3"
  526. #define CONFIG_FSL_SGMII_RISER 1
  527. #define SGMII_RISER_PHY_OFFSET 0x1c
  528. #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
  529. #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
  530. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  531. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  532. #define TSEC1_PHYIDX 0
  533. #define TSEC3_PHYIDX 0
  534. #define CONFIG_ETHPRIME "eTSEC1"
  535. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  536. #endif /* CONFIG_TSEC_ENET */
  537. /*
  538. * Environment
  539. */
  540. #if defined(CONFIG_SYS_RAMBOOT)
  541. #if defined(CONFIG_RAMBOOT_NAND)
  542. #define CONFIG_ENV_IS_IN_NAND 1
  543. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  544. #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
  545. #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
  546. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  547. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  548. #define CONFIG_ENV_SIZE 0x2000
  549. #endif
  550. #else
  551. #define CONFIG_ENV_IS_IN_FLASH 1
  552. #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
  553. #define CONFIG_ENV_ADDR 0xfff80000
  554. #else
  555. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  556. #endif
  557. #define CONFIG_ENV_SIZE 0x2000
  558. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  559. #endif
  560. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  561. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  562. /*
  563. * Command line configuration.
  564. */
  565. #include <config_cmd_default.h>
  566. #define CONFIG_CMD_IRQ
  567. #define CONFIG_CMD_PING
  568. #define CONFIG_CMD_I2C
  569. #define CONFIG_CMD_MII
  570. #define CONFIG_CMD_ELF
  571. #define CONFIG_CMD_IRQ
  572. #define CONFIG_CMD_SETEXPR
  573. #define CONFIG_CMD_REGINFO
  574. #if defined(CONFIG_PCI)
  575. #define CONFIG_CMD_PCI
  576. #define CONFIG_CMD_NET
  577. #endif
  578. #undef CONFIG_WATCHDOG /* watchdog disabled */
  579. #define CONFIG_MMC 1
  580. #ifdef CONFIG_MMC
  581. #define CONFIG_FSL_ESDHC
  582. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  583. #define CONFIG_CMD_MMC
  584. #define CONFIG_GENERIC_MMC
  585. #define CONFIG_CMD_EXT2
  586. #define CONFIG_CMD_FAT
  587. #define CONFIG_DOS_PARTITION
  588. #endif
  589. /*
  590. * Miscellaneous configurable options
  591. */
  592. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  593. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  594. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  595. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  596. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  597. #if defined(CONFIG_CMD_KGDB)
  598. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  599. #else
  600. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  601. #endif
  602. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
  603. + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
  604. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  605. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  606. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  607. /*
  608. * For booting Linux, the board info and command line data
  609. * have to be in the first 16 MB of memory, since this is
  610. * the maximum mapped by the Linux kernel during initialization.
  611. */
  612. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
  613. #if defined(CONFIG_CMD_KGDB)
  614. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  615. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  616. #endif
  617. /*
  618. * Environment Configuration
  619. */
  620. /* The mac addresses for all ethernet interface */
  621. #if defined(CONFIG_TSEC_ENET)
  622. #define CONFIG_HAS_ETH0
  623. #define CONFIG_ETHADDR 00:E0:0C:02:00:FD
  624. #define CONFIG_HAS_ETH1
  625. #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
  626. #define CONFIG_HAS_ETH2
  627. #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
  628. #define CONFIG_HAS_ETH3
  629. #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
  630. #endif
  631. #define CONFIG_IPADDR 192.168.1.254
  632. #define CONFIG_HOSTNAME unknown
  633. #define CONFIG_ROOTPATH /opt/nfsroot
  634. #define CONFIG_BOOTFILE uImage
  635. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  636. #define CONFIG_SERVERIP 192.168.1.1
  637. #define CONFIG_GATEWAYIP 192.168.1.1
  638. #define CONFIG_NETMASK 255.255.255.0
  639. /* default location for tftp and bootm */
  640. #define CONFIG_LOADADDR 1000000
  641. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  642. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  643. #define CONFIG_BAUDRATE 115200
  644. #define CONFIG_EXTRA_ENV_SETTINGS \
  645. "netdev=eth0\0" \
  646. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  647. "tftpflash=tftpboot $loadaddr $uboot; " \
  648. "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  649. "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  650. "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  651. "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  652. "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  653. "consoledev=ttyS0\0" \
  654. "ramdiskaddr=2000000\0" \
  655. "ramdiskfile=8536ds/ramdisk.uboot\0" \
  656. "fdtaddr=c00000\0" \
  657. "fdtfile=8536ds/mpc8536ds.dtb\0" \
  658. "bdev=sda3\0" \
  659. "usb_phy_type=ulpi\0"
  660. #define CONFIG_HDBOOT \
  661. "setenv bootargs root=/dev/$bdev rw " \
  662. "console=$consoledev,$baudrate $othbootargs;" \
  663. "tftp $loadaddr $bootfile;" \
  664. "tftp $fdtaddr $fdtfile;" \
  665. "bootm $loadaddr - $fdtaddr"
  666. #define CONFIG_NFSBOOTCOMMAND \
  667. "setenv bootargs root=/dev/nfs rw " \
  668. "nfsroot=$serverip:$rootpath " \
  669. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  670. "console=$consoledev,$baudrate $othbootargs;" \
  671. "tftp $loadaddr $bootfile;" \
  672. "tftp $fdtaddr $fdtfile;" \
  673. "bootm $loadaddr - $fdtaddr"
  674. #define CONFIG_RAMBOOTCOMMAND \
  675. "setenv bootargs root=/dev/ram rw " \
  676. "console=$consoledev,$baudrate $othbootargs;" \
  677. "tftp $ramdiskaddr $ramdiskfile;" \
  678. "tftp $loadaddr $bootfile;" \
  679. "tftp $fdtaddr $fdtfile;" \
  680. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  681. #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  682. #endif /* __CONFIG_H */