CATcenter.h 27 KB

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  1. /*
  2. * ueberarbeitet durch Christoph Seyfert
  3. *
  4. * (C) Copyright 2004-2005 DENX Software Engineering,
  5. * Wolfgang Grandegger <wg@denx.de>
  6. * (C) Copyright 2003
  7. * DAVE Srl
  8. *
  9. * http://www.dave-tech.it
  10. * http://www.wawnet.biz
  11. * mailto:info@wawnet.biz
  12. *
  13. * Credits: Stefan Roese, Wolfgang Denk
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. /*
  31. * board/config.h - configuration options, board specific
  32. */
  33. #ifndef __CONFIG_H
  34. #define __CONFIG_H
  35. #define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
  36. #define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
  37. #define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
  38. #ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
  39. #define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
  40. #endif
  41. /* Only one of the following two symbols must be defined (default is 25 MHz)
  42. * CONFIG_PPCHAMELEON_CLK_25
  43. * CONFIG_PPCHAMELEON_CLK_33
  44. */
  45. #if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
  46. #define CONFIG_PPCHAMELEON_CLK_25
  47. #endif
  48. #if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
  49. #error "* Two external frequencies (SysClk) are defined! *"
  50. #endif
  51. #undef CONFIG_PPCHAMELEON_SMI712
  52. /*
  53. * Debug stuff
  54. */
  55. #undef __DEBUG_START_FROM_SRAM__
  56. #define __DISABLE_MACHINE_EXCEPTION__
  57. #ifdef __DEBUG_START_FROM_SRAM__
  58. #define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
  59. #endif
  60. /*
  61. * High Level Configuration Options
  62. * (easy to change)
  63. */
  64. #define CONFIG_405EP 1 /* This is a PPC405 CPU */
  65. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  66. #define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
  67. #define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
  68. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  69. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  70. #ifdef CONFIG_PPCHAMELEON_CLK_25
  71. # define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
  72. #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  73. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  74. #else
  75. # error "* External frequency (SysClk) not defined! *"
  76. #endif
  77. #define CONFIG_CONS_INDEX 2 /* Use UART1 */
  78. #define CONFIG_SYS_NS16550
  79. #define CONFIG_SYS_NS16550_SERIAL
  80. #define CONFIG_SYS_NS16550_REG_SIZE 1
  81. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  82. #define CONFIG_BAUDRATE 115200
  83. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  84. #define CONFIG_VERSION_VARIABLE 1 /* add version variable */
  85. #define CONFIG_IDENT_STRING "1"
  86. #undef CONFIG_BOOTARGS
  87. /* Ethernet stuff */
  88. #define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
  89. #define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
  90. #define CONFIG_HAS_ETH1
  91. #define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
  92. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  93. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  94. #define CONFIG_PPC4xx_EMAC
  95. #undef CONFIG_EXT_PHY
  96. #define CONFIG_NET_MULTI 1
  97. #define CONFIG_MII 1 /* MII PHY management */
  98. #ifndef CONFIG_EXT_PHY
  99. #define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
  100. #define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
  101. #else
  102. #define CONFIG_PHY_ADDR 2 /* PHY address */
  103. #endif
  104. #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
  105. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  106. /*
  107. * BOOTP options
  108. */
  109. #define CONFIG_BOOTP_BOOTFILESIZE
  110. #define CONFIG_BOOTP_BOOTPATH
  111. #define CONFIG_BOOTP_GATEWAY
  112. #define CONFIG_BOOTP_HOSTNAME
  113. /*
  114. * Command line configuration.
  115. */
  116. #include <config_cmd_default.h>
  117. #define CONFIG_CMD_DHCP
  118. #define CONFIG_CMD_ELF
  119. #define CONFIG_CMD_EEPROM
  120. #define CONFIG_CMD_I2C
  121. #define CONFIG_CMD_IRQ
  122. #define CONFIG_CMD_JFFS2
  123. #define CONFIG_CMD_MII
  124. #define CONFIG_CMD_NAND
  125. #define CONFIG_CMD_NFS
  126. #define CONFIG_CMD_SNTP
  127. #define CONFIG_MAC_PARTITION
  128. #define CONFIG_DOS_PARTITION
  129. #undef CONFIG_WATCHDOG /* watchdog disabled */
  130. #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
  131. #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
  132. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  133. /*
  134. * Miscellaneous configurable options
  135. */
  136. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  137. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  138. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  139. #ifdef CONFIG_SYS_HUSH_PARSER
  140. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  141. #endif
  142. #if defined(CONFIG_CMD_KGDB)
  143. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  144. #else
  145. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  146. #endif
  147. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  148. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  149. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  150. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  151. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  152. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  153. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  154. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  155. #define CONFIG_SYS_BASE_BAUD 691200
  156. /* The following table includes the supported baudrates */
  157. #define CONFIG_SYS_BAUDRATE_TABLE \
  158. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  159. 57600, 115200, 230400, 460800, 921600 }
  160. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  161. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  162. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  163. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  164. /*-----------------------------------------------------------------------
  165. * NAND-FLASH stuff
  166. *-----------------------------------------------------------------------
  167. */
  168. #define CONFIG_SYS_NAND0_BASE 0xFF400000
  169. #define CONFIG_SYS_NAND1_BASE 0xFF000000
  170. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
  171. #define NAND_BIG_DELAY_US 25
  172. /* For CATcenter there is only NAND on the module */
  173. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
  174. #define NAND_NO_RB
  175. #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
  176. #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
  177. #define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
  178. #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
  179. #define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
  180. #define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
  181. #define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
  182. #define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
  183. #define MACRO_NAND_DISABLE_CE(nandptr) do \
  184. { \
  185. switch((unsigned long)nandptr) \
  186. { \
  187. case CONFIG_SYS_NAND0_BASE: \
  188. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
  189. break; \
  190. case CONFIG_SYS_NAND1_BASE: \
  191. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
  192. break; \
  193. } \
  194. } while(0)
  195. #define MACRO_NAND_ENABLE_CE(nandptr) do \
  196. { \
  197. switch((unsigned long)nandptr) \
  198. { \
  199. case CONFIG_SYS_NAND0_BASE: \
  200. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
  201. break; \
  202. case CONFIG_SYS_NAND1_BASE: \
  203. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
  204. break; \
  205. } \
  206. } while(0)
  207. #define MACRO_NAND_CTL_CLRALE(nandptr) do \
  208. { \
  209. switch((unsigned long)nandptr) \
  210. { \
  211. case CONFIG_SYS_NAND0_BASE: \
  212. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
  213. break; \
  214. case CONFIG_SYS_NAND1_BASE: \
  215. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
  216. break; \
  217. } \
  218. } while(0)
  219. #define MACRO_NAND_CTL_SETALE(nandptr) do \
  220. { \
  221. switch((unsigned long)nandptr) \
  222. { \
  223. case CONFIG_SYS_NAND0_BASE: \
  224. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
  225. break; \
  226. case CONFIG_SYS_NAND1_BASE: \
  227. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
  228. break; \
  229. } \
  230. } while(0)
  231. #define MACRO_NAND_CTL_CLRCLE(nandptr) do \
  232. { \
  233. switch((unsigned long)nandptr) \
  234. { \
  235. case CONFIG_SYS_NAND0_BASE: \
  236. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
  237. break; \
  238. case CONFIG_SYS_NAND1_BASE: \
  239. out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
  240. break; \
  241. } \
  242. } while(0)
  243. #define MACRO_NAND_CTL_SETCLE(nandptr) do { \
  244. switch((unsigned long)nandptr) { \
  245. case CONFIG_SYS_NAND0_BASE: \
  246. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
  247. break; \
  248. case CONFIG_SYS_NAND1_BASE: \
  249. out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
  250. break; \
  251. } \
  252. } while(0)
  253. #ifdef NAND_NO_RB
  254. /* constant delay (see also tR in the datasheet) */
  255. #define NAND_WAIT_READY(nand) do { \
  256. udelay(12); \
  257. } while (0)
  258. #else
  259. /* use the R/B pin */
  260. /* TBD */
  261. #endif
  262. #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
  263. #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
  264. #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
  265. #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
  266. /*-----------------------------------------------------------------------
  267. * PCI stuff
  268. *-----------------------------------------------------------------------
  269. */
  270. #if 0 /* No PCI on CATcenter */
  271. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  272. #define PCI_HOST_FORCE 1 /* configure as pci host */
  273. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  274. #define CONFIG_PCI /* include pci support */
  275. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  276. #undef CONFIG_PCI_PNP /* do pci plug-and-play */
  277. /* resource configuration */
  278. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  279. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
  280. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
  281. #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  282. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  283. #define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
  284. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  285. #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
  286. #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  287. #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  288. #endif /* No PCI */
  289. /*-----------------------------------------------------------------------
  290. * Start addresses for the final memory configuration
  291. * (Set up by the startup code)
  292. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  293. */
  294. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  295. #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
  296. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  297. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  298. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
  299. /*
  300. * For booting Linux, the board info and command line data
  301. * have to be in the first 8 MB of memory, since this is
  302. * the maximum mapped by the Linux kernel during initialization.
  303. */
  304. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  305. /*-----------------------------------------------------------------------
  306. * FLASH organization
  307. */
  308. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  309. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  310. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  311. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
  312. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  313. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  314. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  315. /*
  316. * The following defines are added for buggy IOP480 byte interface.
  317. * All other boards should use the standard values (CPCI405 etc.)
  318. */
  319. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  320. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  321. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  322. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  323. /*-----------------------------------------------------------------------
  324. * Environment Variable setup
  325. */
  326. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  327. #define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
  328. #define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
  329. #define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
  330. #define CONFIG_ENV_SIZE_REDUND 0x2000
  331. #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
  332. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
  333. #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
  334. /*-----------------------------------------------------------------------
  335. * I2C EEPROM (CAT24WC16) for environment
  336. */
  337. #define CONFIG_HARD_I2C /* I2c with hardware support */
  338. #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
  339. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  340. #define CONFIG_SYS_I2C_SLAVE 0x7F
  341. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  342. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  343. /* mask of address bits that overflow into the "EEPROM chip address" */
  344. /*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
  345. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  346. /* 16 byte page write mode using*/
  347. /* last 4 bits of the address */
  348. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  349. /*
  350. * Init Memory Controller:
  351. *
  352. * BR0/1 and OR0/1 (FLASH)
  353. */
  354. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  355. /*-----------------------------------------------------------------------
  356. * External Bus Controller (EBC) Setup
  357. */
  358. /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
  359. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  360. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  361. /* Memory Bank 1 (External SRAM) initialization */
  362. /* Since this must replace NOR Flash, we use the same settings for CS0 */
  363. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  364. #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
  365. /* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
  366. #define CONFIG_SYS_EBC_PB2AP 0x92015480
  367. #define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
  368. /* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
  369. #define CONFIG_SYS_EBC_PB3AP 0x92015480
  370. #define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
  371. #ifdef CONFIG_PPCHAMELEON_SMI712
  372. /*
  373. * Video console (graphic: SMI LynxEM)
  374. */
  375. #define CONFIG_VIDEO
  376. #define CONFIG_CFB_CONSOLE
  377. #define CONFIG_VIDEO_SMI_LYNXEM
  378. #define CONFIG_VIDEO_LOGO
  379. /*#define CONFIG_VIDEO_BMP_LOGO*/
  380. #define CONFIG_CONSOLE_EXTRA_INFO
  381. #define CONFIG_VGA_AS_SINGLE_DEVICE
  382. /* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
  383. #define CONFIG_SYS_ISA_IO 0xE8000000
  384. /* see also drivers/video/videomodes.c */
  385. #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
  386. #endif
  387. /*-----------------------------------------------------------------------
  388. * FPGA stuff
  389. */
  390. /* FPGA internal regs */
  391. #define CONFIG_SYS_FPGA_MODE 0x00
  392. #define CONFIG_SYS_FPGA_STATUS 0x02
  393. #define CONFIG_SYS_FPGA_TS 0x04
  394. #define CONFIG_SYS_FPGA_TS_LOW 0x06
  395. #define CONFIG_SYS_FPGA_TS_CAP0 0x10
  396. #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
  397. #define CONFIG_SYS_FPGA_TS_CAP1 0x14
  398. #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
  399. #define CONFIG_SYS_FPGA_TS_CAP2 0x18
  400. #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
  401. #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
  402. #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
  403. /* FPGA Mode Reg */
  404. #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
  405. #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
  406. #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
  407. #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
  408. /* FPGA Status Reg */
  409. #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
  410. #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
  411. #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
  412. #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
  413. #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
  414. #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
  415. #define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
  416. /* FPGA program pin configuration */
  417. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  418. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  419. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  420. #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
  421. #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
  422. /*-----------------------------------------------------------------------
  423. * Definitions for initial stack pointer and data area (in data cache)
  424. */
  425. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  426. #define CONFIG_SYS_TEMP_STACK_OCM 1
  427. /* On Chip Memory location */
  428. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  429. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  430. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
  431. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  432. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  433. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  434. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  435. /*-----------------------------------------------------------------------
  436. * Definitions for GPIO setup (PPC405EP specific)
  437. *
  438. * GPIO0[0] - External Bus Controller BLAST output
  439. * GPIO0[1-9] - Instruction trace outputs -> GPIO
  440. * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
  441. * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
  442. * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
  443. * GPIO0[24-27] - UART0 control signal inputs/outputs
  444. * GPIO0[28-29] - UART1 data signal input/output
  445. * GPIO0[30] - EMAC0 input
  446. * GPIO0[31] - EMAC1 reject packet as output
  447. */
  448. #define CONFIG_SYS_GPIO0_OSRL 0x40000550
  449. #define CONFIG_SYS_GPIO0_OSRH 0x00000110
  450. #define CONFIG_SYS_GPIO0_ISR1L 0x00000000
  451. /*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
  452. #define CONFIG_SYS_GPIO0_ISR1H 0x15555444
  453. #define CONFIG_SYS_GPIO0_TSRL 0x00000000
  454. #define CONFIG_SYS_GPIO0_TSRH 0x00000000
  455. #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
  456. #define CONFIG_NO_SERIAL_EEPROM
  457. /*--------------------------------------------------------------------*/
  458. #ifdef CONFIG_NO_SERIAL_EEPROM
  459. /*
  460. !-----------------------------------------------------------------------
  461. ! Defines for entry options.
  462. ! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
  463. ! are plugged in the board will be utilized as non-ECC DIMMs.
  464. !-----------------------------------------------------------------------
  465. */
  466. #undef AUTO_MEMORY_CONFIG
  467. #define DIMM_READ_ADDR 0xAB
  468. #define DIMM_WRITE_ADDR 0xAA
  469. /* Defines for CPC0_PLLMR1 Register fields */
  470. #define PLL_ACTIVE 0x80000000
  471. #define CPC0_PLLMR1_SSCS 0x80000000
  472. #define PLL_RESET 0x40000000
  473. #define CPC0_PLLMR1_PLLR 0x40000000
  474. /* Feedback multiplier */
  475. #define PLL_FBKDIV 0x00F00000
  476. #define CPC0_PLLMR1_FBDV 0x00F00000
  477. #define PLL_FBKDIV_16 0x00000000
  478. #define PLL_FBKDIV_1 0x00100000
  479. #define PLL_FBKDIV_2 0x00200000
  480. #define PLL_FBKDIV_3 0x00300000
  481. #define PLL_FBKDIV_4 0x00400000
  482. #define PLL_FBKDIV_5 0x00500000
  483. #define PLL_FBKDIV_6 0x00600000
  484. #define PLL_FBKDIV_7 0x00700000
  485. #define PLL_FBKDIV_8 0x00800000
  486. #define PLL_FBKDIV_9 0x00900000
  487. #define PLL_FBKDIV_10 0x00A00000
  488. #define PLL_FBKDIV_11 0x00B00000
  489. #define PLL_FBKDIV_12 0x00C00000
  490. #define PLL_FBKDIV_13 0x00D00000
  491. #define PLL_FBKDIV_14 0x00E00000
  492. #define PLL_FBKDIV_15 0x00F00000
  493. /* Forward A divisor */
  494. #define PLL_FWDDIVA 0x00070000
  495. #define CPC0_PLLMR1_FWDVA 0x00070000
  496. #define PLL_FWDDIVA_8 0x00000000
  497. #define PLL_FWDDIVA_7 0x00010000
  498. #define PLL_FWDDIVA_6 0x00020000
  499. #define PLL_FWDDIVA_5 0x00030000
  500. #define PLL_FWDDIVA_4 0x00040000
  501. #define PLL_FWDDIVA_3 0x00050000
  502. #define PLL_FWDDIVA_2 0x00060000
  503. #define PLL_FWDDIVA_1 0x00070000
  504. /* Forward B divisor */
  505. #define PLL_FWDDIVB 0x00007000
  506. #define CPC0_PLLMR1_FWDVB 0x00007000
  507. #define PLL_FWDDIVB_8 0x00000000
  508. #define PLL_FWDDIVB_7 0x00001000
  509. #define PLL_FWDDIVB_6 0x00002000
  510. #define PLL_FWDDIVB_5 0x00003000
  511. #define PLL_FWDDIVB_4 0x00004000
  512. #define PLL_FWDDIVB_3 0x00005000
  513. #define PLL_FWDDIVB_2 0x00006000
  514. #define PLL_FWDDIVB_1 0x00007000
  515. /* PLL tune bits */
  516. #define PLL_TUNE_MASK 0x000003FF
  517. #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
  518. #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
  519. #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
  520. #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
  521. #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
  522. #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
  523. #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
  524. /* Defines for CPC0_PLLMR0 Register fields */
  525. /* CPU divisor */
  526. #define PLL_CPUDIV 0x00300000
  527. #define CPC0_PLLMR0_CCDV 0x00300000
  528. #define PLL_CPUDIV_1 0x00000000
  529. #define PLL_CPUDIV_2 0x00100000
  530. #define PLL_CPUDIV_3 0x00200000
  531. #define PLL_CPUDIV_4 0x00300000
  532. /* PLB divisor */
  533. #define PLL_PLBDIV 0x00030000
  534. #define CPC0_PLLMR0_CBDV 0x00030000
  535. #define PLL_PLBDIV_1 0x00000000
  536. #define PLL_PLBDIV_2 0x00010000
  537. #define PLL_PLBDIV_3 0x00020000
  538. #define PLL_PLBDIV_4 0x00030000
  539. /* OPB divisor */
  540. #define PLL_OPBDIV 0x00003000
  541. #define CPC0_PLLMR0_OPDV 0x00003000
  542. #define PLL_OPBDIV_1 0x00000000
  543. #define PLL_OPBDIV_2 0x00001000
  544. #define PLL_OPBDIV_3 0x00002000
  545. #define PLL_OPBDIV_4 0x00003000
  546. /* EBC divisor */
  547. #define PLL_EXTBUSDIV 0x00000300
  548. #define CPC0_PLLMR0_EPDV 0x00000300
  549. #define PLL_EXTBUSDIV_2 0x00000000
  550. #define PLL_EXTBUSDIV_3 0x00000100
  551. #define PLL_EXTBUSDIV_4 0x00000200
  552. #define PLL_EXTBUSDIV_5 0x00000300
  553. /* MAL divisor */
  554. #define PLL_MALDIV 0x00000030
  555. #define CPC0_PLLMR0_MPDV 0x00000030
  556. #define PLL_MALDIV_1 0x00000000
  557. #define PLL_MALDIV_2 0x00000010
  558. #define PLL_MALDIV_3 0x00000020
  559. #define PLL_MALDIV_4 0x00000030
  560. /* PCI divisor */
  561. #define PLL_PCIDIV 0x00000003
  562. #define CPC0_PLLMR0_PPFD 0x00000003
  563. #define PLL_PCIDIV_1 0x00000000
  564. #define PLL_PCIDIV_2 0x00000001
  565. #define PLL_PCIDIV_3 0x00000002
  566. #define PLL_PCIDIV_4 0x00000003
  567. #ifdef CONFIG_PPCHAMELEON_CLK_25
  568. /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
  569. #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
  570. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  571. PLL_MALDIV_1 | PLL_PCIDIV_4)
  572. #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
  573. PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
  574. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  575. #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  576. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  577. PLL_MALDIV_1 | PLL_PCIDIV_4)
  578. #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
  579. PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
  580. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  581. #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  582. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  583. PLL_MALDIV_1 | PLL_PCIDIV_4)
  584. #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
  585. PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
  586. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  587. #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  588. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  589. PLL_MALDIV_1 | PLL_PCIDIV_2)
  590. #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
  591. PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
  592. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  593. #elif (defined (CONFIG_PPCHAMELEON_CLK_33))
  594. /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
  595. #define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
  596. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  597. PLL_MALDIV_1 | PLL_PCIDIV_4)
  598. #define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
  599. PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
  600. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  601. #define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  602. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  603. PLL_MALDIV_1 | PLL_PCIDIV_4)
  604. #define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
  605. PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
  606. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  607. #define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
  608. PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
  609. PLL_MALDIV_1 | PLL_PCIDIV_4)
  610. #define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
  611. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  612. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
  613. #define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
  614. PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
  615. PLL_MALDIV_1 | PLL_PCIDIV_2)
  616. #define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
  617. PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
  618. PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
  619. #else
  620. #error "* External frequency (SysClk) not defined! *"
  621. #endif
  622. #if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
  623. /* Model HI */
  624. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
  625. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
  626. #define CONFIG_SYS_OPB_FREQ 55555555
  627. /* Model ME */
  628. #elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
  629. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
  630. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
  631. #define CONFIG_SYS_OPB_FREQ 66666666
  632. #else
  633. /* Model BA (default) */
  634. #define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
  635. #define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
  636. #define CONFIG_SYS_OPB_FREQ 66666666
  637. #endif
  638. #endif /* CONFIG_NO_SERIAL_EEPROM */
  639. #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
  640. #define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
  641. /*
  642. * JFFS2 partitions
  643. *
  644. */
  645. /* No command line, one static partition */
  646. #undef CONFIG_CMD_MTDPARTS
  647. #define CONFIG_JFFS2_DEV "nand"
  648. #define CONFIG_JFFS2_PART_SIZE 0x00200000
  649. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  650. /* mtdparts command line support
  651. *
  652. * Note: fake mtd_id used, no linux mtd map file
  653. */
  654. /*
  655. #define CONFIG_CMD_MTDPARTS
  656. #define MTDIDS_DEFAULT "nand0=catcenter"
  657. #define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
  658. */
  659. #endif /* __CONFIG_H */