mb86r0xgdc.c 4.3 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Matthias Weisser <weisserm@arcor.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic
  25. * controller.
  26. */
  27. #include <common.h>
  28. #include <malloc.h>
  29. #include <asm/io.h>
  30. #include <asm/arch/hardware.h>
  31. #include <video_fb.h>
  32. #include "videomodes.h"
  33. /*
  34. * 4MB (at the end of system RAM)
  35. */
  36. #define VIDEO_MEM_SIZE 0x400000
  37. #define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
  38. /*
  39. * Graphic Device
  40. */
  41. static GraphicDevice mb86r0x;
  42. static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr,
  43. u32 *videomem)
  44. {
  45. struct ctfb_res_modes var_mode;
  46. u32 dcm1, dcm2, dcm3;
  47. u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;
  48. u8 hsw, vsw;
  49. u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;
  50. u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
  51. unsigned long div;
  52. int bpp;
  53. u32 i;
  54. bpp = video_get_params(&var_mode, modestr);
  55. if (bpp == 0) {
  56. var_mode.xres = 640;
  57. var_mode.yres = 480;
  58. var_mode.pixclock = 39721; /* 25MHz */
  59. var_mode.left_margin = 48;
  60. var_mode.right_margin = 16;
  61. var_mode.upper_margin = 33;
  62. var_mode.lower_margin = 10;
  63. var_mode.hsync_len = 96;
  64. var_mode.vsync_len = 2;
  65. var_mode.sync = 0;
  66. var_mode.vmode = 0;
  67. bpp = 15;
  68. }
  69. /* Fill memory with white */
  70. for (i = 0; i < var_mode.xres * var_mode.yres / 2; i++)
  71. *videomem++ = 0xFFFFFFFF;
  72. mb86r0x.winSizeX = var_mode.xres;
  73. mb86r0x.winSizeY = var_mode.yres;
  74. /* LCD base clock is ~ 660MHZ. We do calculations in kHz */
  75. div = 660000 / (1000000000L / var_mode.pixclock);
  76. if (div > 64)
  77. div = 64;
  78. if (0 == div)
  79. div = 1;
  80. dcm1 = (div - 1) << 8;
  81. dcm2 = 0x00000000;
  82. if (var_mode.sync & FB_SYNC_CLK_INV)
  83. dcm3 = 0x00000100;
  84. else
  85. dcm3 = 0x00000000;
  86. htp = var_mode.left_margin + var_mode.xres +
  87. var_mode.hsync_len + var_mode.right_margin;
  88. hdp = var_mode.xres;
  89. hdb = var_mode.xres;
  90. hsp = var_mode.xres + var_mode.right_margin;
  91. hsw = var_mode.hsync_len;
  92. vsw = var_mode.vsync_len;
  93. vtr = var_mode.upper_margin + var_mode.yres +
  94. var_mode.vsync_len + var_mode.lower_margin;
  95. vsp = var_mode.yres + var_mode.lower_margin;
  96. vdp = var_mode.yres;
  97. l2m = ((var_mode.yres - 1) << (0)) |
  98. (((var_mode.xres * 2) / 64) << (16)) |
  99. ((1) << (31));
  100. l2em = (1 << 0) | (1 << 1);
  101. l2oa0 = mb86r0x.frameAdrs;
  102. l2da0 = mb86r0x.frameAdrs;
  103. l2oa1 = mb86r0x.frameAdrs;
  104. l2da1 = mb86r0x.frameAdrs;
  105. l2dx = 0;
  106. l2dy = 0;
  107. l2wx = 0;
  108. l2wy = 0;
  109. l2ww = var_mode.xres;
  110. l2wh = var_mode.yres - 1;
  111. writel(dcm1, &dsp->dcm1);
  112. writel(dcm2, &dsp->dcm2);
  113. writel(dcm3, &dsp->dcm3);
  114. writew(htp, &dsp->htp);
  115. writew(hdp, &dsp->hdp);
  116. writew(hdb, &dsp->hdb);
  117. writew(hsp, &dsp->hsp);
  118. writeb(hsw, &dsp->hsw);
  119. writeb(vsw, &dsp->vsw);
  120. writew(vtr, &dsp->vtr);
  121. writew(vsp, &dsp->vsp);
  122. writew(vdp, &dsp->vdp);
  123. writel(l2m, &dsp->l2m);
  124. writel(l2em, &dsp->l2em);
  125. writel(l2oa0, &dsp->l2oa0);
  126. writel(l2da0, &dsp->l2da0);
  127. writel(l2oa1, &dsp->l2oa1);
  128. writel(l2da1, &dsp->l2da1);
  129. writew(l2dx, &dsp->l2dx);
  130. writew(l2dy, &dsp->l2dy);
  131. writew(l2wx, &dsp->l2wx);
  132. writew(l2wy, &dsp->l2wy);
  133. writew(l2ww, &dsp->l2ww);
  134. writew(l2wh, &dsp->l2wh);
  135. writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1);
  136. }
  137. void *video_hw_init(void)
  138. {
  139. struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE;
  140. GraphicDevice *pGD = &mb86r0x;
  141. char *s;
  142. u32 *vid;
  143. memset(pGD, 0, sizeof(GraphicDevice));
  144. pGD->gdfIndex = GDF_15BIT_555RGB;
  145. pGD->gdfBytesPP = 2;
  146. pGD->memSize = VIDEO_MEM_SIZE;
  147. pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
  148. vid = (u32 *)pGD->frameAdrs;
  149. s = getenv("videomode");
  150. if (s != NULL)
  151. dsp_init(&gdc->dsp0, s, vid);
  152. s = getenv("videomode1");
  153. if (s != NULL)
  154. dsp_init(&gdc->dsp1, s, vid);
  155. return pGD;
  156. }