musb_hcd.c 31 KB

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  1. /*
  2. * Mentor USB OTG Core host controller driver.
  3. *
  4. * Copyright (c) 2008 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. *
  21. * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments
  22. */
  23. #include <common.h>
  24. #include "musb_hcd.h"
  25. /* MSC control transfers */
  26. #define USB_MSC_BBB_RESET 0xFF
  27. #define USB_MSC_BBB_GET_MAX_LUN 0xFE
  28. /* Endpoint configuration information */
  29. static struct musb_epinfo epinfo[3] = {
  30. {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */
  31. {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */
  32. {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */
  33. };
  34. /* --- Virtual Root Hub ---------------------------------------------------- */
  35. #ifdef MUSB_NO_MULTIPOINT
  36. static int rh_devnum;
  37. static u32 port_status;
  38. /* Device descriptor */
  39. static u8 root_hub_dev_des[] = {
  40. 0x12, /* __u8 bLength; */
  41. 0x01, /* __u8 bDescriptorType; Device */
  42. 0x00, /* __u16 bcdUSB; v1.1 */
  43. 0x02,
  44. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  45. 0x00, /* __u8 bDeviceSubClass; */
  46. 0x00, /* __u8 bDeviceProtocol; */
  47. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  48. 0x00, /* __u16 idVendor; */
  49. 0x00,
  50. 0x00, /* __u16 idProduct; */
  51. 0x00,
  52. 0x00, /* __u16 bcdDevice; */
  53. 0x00,
  54. 0x00, /* __u8 iManufacturer; */
  55. 0x01, /* __u8 iProduct; */
  56. 0x00, /* __u8 iSerialNumber; */
  57. 0x01 /* __u8 bNumConfigurations; */
  58. };
  59. /* Configuration descriptor */
  60. static u8 root_hub_config_des[] = {
  61. 0x09, /* __u8 bLength; */
  62. 0x02, /* __u8 bDescriptorType; Configuration */
  63. 0x19, /* __u16 wTotalLength; */
  64. 0x00,
  65. 0x01, /* __u8 bNumInterfaces; */
  66. 0x01, /* __u8 bConfigurationValue; */
  67. 0x00, /* __u8 iConfiguration; */
  68. 0x40, /* __u8 bmAttributes;
  69. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  70. 0x00, /* __u8 MaxPower; */
  71. /* interface */
  72. 0x09, /* __u8 if_bLength; */
  73. 0x04, /* __u8 if_bDescriptorType; Interface */
  74. 0x00, /* __u8 if_bInterfaceNumber; */
  75. 0x00, /* __u8 if_bAlternateSetting; */
  76. 0x01, /* __u8 if_bNumEndpoints; */
  77. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  78. 0x00, /* __u8 if_bInterfaceSubClass; */
  79. 0x00, /* __u8 if_bInterfaceProtocol; */
  80. 0x00, /* __u8 if_iInterface; */
  81. /* endpoint */
  82. 0x07, /* __u8 ep_bLength; */
  83. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  84. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  85. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  86. 0x00, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  87. 0x02,
  88. 0xff /* __u8 ep_bInterval; 255 ms */
  89. };
  90. static unsigned char root_hub_str_index0[] = {
  91. 0x04, /* __u8 bLength; */
  92. 0x03, /* __u8 bDescriptorType; String-descriptor */
  93. 0x09, /* __u8 lang ID */
  94. 0x04, /* __u8 lang ID */
  95. };
  96. static unsigned char root_hub_str_index1[] = {
  97. 0x1c, /* __u8 bLength; */
  98. 0x03, /* __u8 bDescriptorType; String-descriptor */
  99. 'M', /* __u8 Unicode */
  100. 0, /* __u8 Unicode */
  101. 'U', /* __u8 Unicode */
  102. 0, /* __u8 Unicode */
  103. 'S', /* __u8 Unicode */
  104. 0, /* __u8 Unicode */
  105. 'B', /* __u8 Unicode */
  106. 0, /* __u8 Unicode */
  107. ' ', /* __u8 Unicode */
  108. 0, /* __u8 Unicode */
  109. 'R', /* __u8 Unicode */
  110. 0, /* __u8 Unicode */
  111. 'o', /* __u8 Unicode */
  112. 0, /* __u8 Unicode */
  113. 'o', /* __u8 Unicode */
  114. 0, /* __u8 Unicode */
  115. 't', /* __u8 Unicode */
  116. 0, /* __u8 Unicode */
  117. ' ', /* __u8 Unicode */
  118. 0, /* __u8 Unicode */
  119. 'H', /* __u8 Unicode */
  120. 0, /* __u8 Unicode */
  121. 'u', /* __u8 Unicode */
  122. 0, /* __u8 Unicode */
  123. 'b', /* __u8 Unicode */
  124. 0, /* __u8 Unicode */
  125. };
  126. #endif
  127. /*
  128. * This function writes the data toggle value.
  129. */
  130. static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out)
  131. {
  132. u16 toggle = usb_gettoggle(dev, ep, dir_out);
  133. u16 csr;
  134. if (dir_out) {
  135. csr = readw(&musbr->txcsr);
  136. if (!toggle) {
  137. if (csr & MUSB_TXCSR_MODE)
  138. csr = MUSB_TXCSR_CLRDATATOG;
  139. else
  140. csr = 0;
  141. writew(csr, &musbr->txcsr);
  142. } else {
  143. csr |= MUSB_TXCSR_H_WR_DATATOGGLE;
  144. writew(csr, &musbr->txcsr);
  145. csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT);
  146. writew(csr, &musbr->txcsr);
  147. }
  148. } else {
  149. if (!toggle) {
  150. csr = readw(&musbr->txcsr);
  151. if (csr & MUSB_TXCSR_MODE)
  152. csr = MUSB_RXCSR_CLRDATATOG;
  153. else
  154. csr = 0;
  155. writew(csr, &musbr->rxcsr);
  156. } else {
  157. csr = readw(&musbr->rxcsr);
  158. csr |= MUSB_RXCSR_H_WR_DATATOGGLE;
  159. writew(csr, &musbr->rxcsr);
  160. csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE);
  161. writew(csr, &musbr->rxcsr);
  162. }
  163. }
  164. }
  165. /*
  166. * This function checks if RxStall has occured on the endpoint. If a RxStall
  167. * has occured, the RxStall is cleared and 1 is returned. If RxStall has
  168. * not occured, 0 is returned.
  169. */
  170. static u8 check_stall(u8 ep, u8 dir_out)
  171. {
  172. u16 csr;
  173. /* For endpoint 0 */
  174. if (!ep) {
  175. csr = readw(&musbr->txcsr);
  176. if (csr & MUSB_CSR0_H_RXSTALL) {
  177. csr &= ~MUSB_CSR0_H_RXSTALL;
  178. writew(csr, &musbr->txcsr);
  179. return 1;
  180. }
  181. } else { /* For non-ep0 */
  182. if (dir_out) { /* is it tx ep */
  183. csr = readw(&musbr->txcsr);
  184. if (csr & MUSB_TXCSR_H_RXSTALL) {
  185. csr &= ~MUSB_TXCSR_H_RXSTALL;
  186. writew(csr, &musbr->txcsr);
  187. return 1;
  188. }
  189. } else { /* is it rx ep */
  190. csr = readw(&musbr->rxcsr);
  191. if (csr & MUSB_RXCSR_H_RXSTALL) {
  192. csr &= ~MUSB_RXCSR_H_RXSTALL;
  193. writew(csr, &musbr->rxcsr);
  194. return 1;
  195. }
  196. }
  197. }
  198. return 0;
  199. }
  200. /*
  201. * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout
  202. * error and -2 for stall.
  203. */
  204. static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
  205. {
  206. u16 csr;
  207. int result = 1;
  208. int timeout = CONFIG_MUSB_TIMEOUT;
  209. while (result > 0) {
  210. csr = readw(&musbr->txcsr);
  211. if (csr & MUSB_CSR0_H_ERROR) {
  212. csr &= ~MUSB_CSR0_H_ERROR;
  213. writew(csr, &musbr->txcsr);
  214. dev->status = USB_ST_CRC_ERR;
  215. result = -1;
  216. break;
  217. }
  218. switch (bit_mask) {
  219. case MUSB_CSR0_TXPKTRDY:
  220. if (!(csr & MUSB_CSR0_TXPKTRDY)) {
  221. if (check_stall(MUSB_CONTROL_EP, 0)) {
  222. dev->status = USB_ST_STALLED;
  223. result = -2;
  224. } else
  225. result = 0;
  226. }
  227. break;
  228. case MUSB_CSR0_RXPKTRDY:
  229. if (check_stall(MUSB_CONTROL_EP, 0)) {
  230. dev->status = USB_ST_STALLED;
  231. result = -2;
  232. } else
  233. if (csr & MUSB_CSR0_RXPKTRDY)
  234. result = 0;
  235. break;
  236. case MUSB_CSR0_H_REQPKT:
  237. if (!(csr & MUSB_CSR0_H_REQPKT)) {
  238. if (check_stall(MUSB_CONTROL_EP, 0)) {
  239. dev->status = USB_ST_STALLED;
  240. result = -2;
  241. } else
  242. result = 0;
  243. }
  244. break;
  245. }
  246. /* Check the timeout */
  247. if (--timeout)
  248. udelay(1);
  249. else {
  250. dev->status = USB_ST_CRC_ERR;
  251. result = -1;
  252. break;
  253. }
  254. }
  255. return result;
  256. }
  257. /*
  258. * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
  259. */
  260. static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
  261. {
  262. u16 csr;
  263. int timeout = CONFIG_MUSB_TIMEOUT;
  264. do {
  265. if (check_stall(ep, 1)) {
  266. dev->status = USB_ST_STALLED;
  267. return 0;
  268. }
  269. csr = readw(&musbr->txcsr);
  270. if (csr & MUSB_TXCSR_H_ERROR) {
  271. dev->status = USB_ST_CRC_ERR;
  272. return 0;
  273. }
  274. /* Check the timeout */
  275. if (--timeout)
  276. udelay(1);
  277. else {
  278. dev->status = USB_ST_CRC_ERR;
  279. return -1;
  280. }
  281. } while (csr & MUSB_TXCSR_TXPKTRDY);
  282. return 1;
  283. }
  284. /*
  285. * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
  286. */
  287. static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
  288. {
  289. u16 csr;
  290. int timeout = CONFIG_MUSB_TIMEOUT;
  291. do {
  292. if (check_stall(ep, 0)) {
  293. dev->status = USB_ST_STALLED;
  294. return 0;
  295. }
  296. csr = readw(&musbr->rxcsr);
  297. if (csr & MUSB_RXCSR_H_ERROR) {
  298. dev->status = USB_ST_CRC_ERR;
  299. return 0;
  300. }
  301. /* Check the timeout */
  302. if (--timeout)
  303. udelay(1);
  304. else {
  305. dev->status = USB_ST_CRC_ERR;
  306. return -1;
  307. }
  308. } while (!(csr & MUSB_RXCSR_RXPKTRDY));
  309. return 1;
  310. }
  311. /*
  312. * This function performs the setup phase of the control transfer
  313. */
  314. static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup)
  315. {
  316. int result;
  317. u16 csr;
  318. /* write the control request to ep0 fifo */
  319. write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup);
  320. /* enable transfer of setup packet */
  321. csr = readw(&musbr->txcsr);
  322. csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT);
  323. writew(csr, &musbr->txcsr);
  324. /* wait until the setup packet is transmitted */
  325. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  326. dev->act_len = 0;
  327. return result;
  328. }
  329. /*
  330. * This function handles the control transfer in data phase
  331. */
  332. static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer)
  333. {
  334. u16 csr;
  335. u32 rxlen = 0;
  336. u32 nextlen = 0;
  337. u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
  338. u8 *rxbuff = (u8 *)buffer;
  339. u8 rxedlength;
  340. int result;
  341. while (rxlen < len) {
  342. /* Determine the next read length */
  343. nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen);
  344. /* Set the ReqPkt bit */
  345. csr = readw(&musbr->txcsr);
  346. writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr);
  347. result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY);
  348. if (result < 0)
  349. return result;
  350. /* Actual number of bytes received by usb */
  351. rxedlength = readb(&musbr->rxcount);
  352. /* Read the data from the RxFIFO */
  353. read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]);
  354. /* Clear the RxPktRdy Bit */
  355. csr = readw(&musbr->txcsr);
  356. csr &= ~MUSB_CSR0_RXPKTRDY;
  357. writew(csr, &musbr->txcsr);
  358. /* short packet? */
  359. if (rxedlength != nextlen) {
  360. dev->act_len += rxedlength;
  361. break;
  362. }
  363. rxlen += nextlen;
  364. dev->act_len = rxlen;
  365. }
  366. return 0;
  367. }
  368. /*
  369. * This function handles the control transfer out data phase
  370. */
  371. static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer)
  372. {
  373. u16 csr;
  374. u32 txlen = 0;
  375. u32 nextlen = 0;
  376. u8 maxpktsize = (1 << dev->maxpacketsize) * 8;
  377. u8 *txbuff = (u8 *)buffer;
  378. int result = 0;
  379. while (txlen < len) {
  380. /* Determine the next write length */
  381. nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen);
  382. /* Load the data to send in FIFO */
  383. write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]);
  384. /* Set TXPKTRDY bit */
  385. csr = readw(&musbr->txcsr);
  386. writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY,
  387. &musbr->txcsr);
  388. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  389. if (result < 0)
  390. break;
  391. txlen += nextlen;
  392. dev->act_len = txlen;
  393. }
  394. return result;
  395. }
  396. /*
  397. * This function handles the control transfer out status phase
  398. */
  399. static int ctrlreq_out_status_phase(struct usb_device *dev)
  400. {
  401. u16 csr;
  402. int result;
  403. /* Set the StatusPkt bit */
  404. csr = readw(&musbr->txcsr);
  405. csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY |
  406. MUSB_CSR0_H_STATUSPKT);
  407. writew(csr, &musbr->txcsr);
  408. /* Wait until TXPKTRDY bit is cleared */
  409. result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY);
  410. return result;
  411. }
  412. /*
  413. * This function handles the control transfer in status phase
  414. */
  415. static int ctrlreq_in_status_phase(struct usb_device *dev)
  416. {
  417. u16 csr;
  418. int result;
  419. /* Set the StatusPkt bit and ReqPkt bit */
  420. csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT;
  421. writew(csr, &musbr->txcsr);
  422. result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT);
  423. /* clear StatusPkt bit and RxPktRdy bit */
  424. csr = readw(&musbr->txcsr);
  425. csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT);
  426. writew(csr, &musbr->txcsr);
  427. return result;
  428. }
  429. /*
  430. * determines the speed of the device (High/Full/Slow)
  431. */
  432. static u8 get_dev_speed(struct usb_device *dev)
  433. {
  434. return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH :
  435. ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW :
  436. MUSB_TYPE_SPEED_FULL);
  437. }
  438. /*
  439. * configure the hub address and the port address.
  440. */
  441. static void config_hub_port(struct usb_device *dev, u8 ep)
  442. {
  443. u8 chid;
  444. u8 hub;
  445. /* Find out the nearest parent which is high speed */
  446. while (dev->parent->parent != NULL)
  447. if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH)
  448. dev = dev->parent;
  449. else
  450. break;
  451. /* determine the port address at that hub */
  452. hub = dev->parent->devnum;
  453. for (chid = 0; chid < USB_MAXCHILDREN; chid++)
  454. if (dev->parent->children[chid] == dev)
  455. break;
  456. #ifndef MUSB_NO_MULTIPOINT
  457. /* configure the hub address and the port address */
  458. writeb(hub, &musbr->tar[ep].txhubaddr);
  459. writeb((chid + 1), &musbr->tar[ep].txhubport);
  460. writeb(hub, &musbr->tar[ep].rxhubaddr);
  461. writeb((chid + 1), &musbr->tar[ep].rxhubport);
  462. #endif
  463. }
  464. #ifdef MUSB_NO_MULTIPOINT
  465. static void musb_port_reset(int do_reset)
  466. {
  467. u8 power = readb(&musbr->power);
  468. if (do_reset) {
  469. power &= 0xf0;
  470. writeb(power | MUSB_POWER_RESET, &musbr->power);
  471. port_status |= USB_PORT_STAT_RESET;
  472. port_status &= ~USB_PORT_STAT_ENABLE;
  473. udelay(30000);
  474. } else {
  475. writeb(power & ~MUSB_POWER_RESET, &musbr->power);
  476. power = readb(&musbr->power);
  477. if (power & MUSB_POWER_HSMODE)
  478. port_status |= USB_PORT_STAT_HIGH_SPEED;
  479. port_status &= ~(USB_PORT_STAT_RESET | (USB_PORT_STAT_C_CONNECTION << 16));
  480. port_status |= USB_PORT_STAT_ENABLE
  481. | (USB_PORT_STAT_C_RESET << 16)
  482. | (USB_PORT_STAT_C_ENABLE << 16);
  483. }
  484. }
  485. /*
  486. * root hub control
  487. */
  488. static int musb_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  489. void *buffer, int transfer_len,
  490. struct devrequest *cmd)
  491. {
  492. int leni = transfer_len;
  493. int len = 0;
  494. int stat = 0;
  495. u32 datab[4];
  496. u8 *data_buf = (u8 *) datab;
  497. u16 bmRType_bReq;
  498. u16 wValue;
  499. u16 wIndex;
  500. u16 wLength;
  501. u16 int_usb;
  502. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  503. debug("Root-Hub submit IRQ: NOT implemented\n");
  504. return 0;
  505. }
  506. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  507. wValue = swap_16(cmd->value);
  508. wIndex = swap_16(cmd->index);
  509. wLength = swap_16(cmd->length);
  510. debug("--- HUB ----------------------------------------\n");
  511. debug("submit rh urb, req=%x val=%#x index=%#x len=%d\n",
  512. bmRType_bReq, wValue, wIndex, wLength);
  513. debug("------------------------------------------------\n");
  514. switch (bmRType_bReq) {
  515. case RH_GET_STATUS:
  516. debug("RH_GET_STATUS\n");
  517. *(__u16 *) data_buf = swap_16(1);
  518. len = 2;
  519. break;
  520. case RH_GET_STATUS | RH_INTERFACE:
  521. debug("RH_GET_STATUS | RH_INTERFACE\n");
  522. *(__u16 *) data_buf = swap_16(0);
  523. len = 2;
  524. break;
  525. case RH_GET_STATUS | RH_ENDPOINT:
  526. debug("RH_GET_STATUS | RH_ENDPOINT\n");
  527. *(__u16 *) data_buf = swap_16(0);
  528. len = 2;
  529. break;
  530. case RH_GET_STATUS | RH_CLASS:
  531. debug("RH_GET_STATUS | RH_CLASS\n");
  532. *(__u32 *) data_buf = swap_32(0);
  533. len = 4;
  534. break;
  535. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  536. debug("RH_GET_STATUS | RH_OTHER | RH_CLASS\n");
  537. int_usb = readw(&musbr->intrusb);
  538. if (int_usb & MUSB_INTR_CONNECT) {
  539. port_status |= USB_PORT_STAT_CONNECTION
  540. | (USB_PORT_STAT_C_CONNECTION << 16);
  541. port_status |= USB_PORT_STAT_HIGH_SPEED
  542. | USB_PORT_STAT_ENABLE;
  543. }
  544. if (port_status & USB_PORT_STAT_RESET)
  545. musb_port_reset(0);
  546. *(__u32 *) data_buf = swap_32(port_status);
  547. len = 4;
  548. break;
  549. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  550. debug("RH_CLEAR_FEATURE | RH_ENDPOINT\n");
  551. switch (wValue) {
  552. case RH_ENDPOINT_STALL:
  553. debug("C_HUB_ENDPOINT_STALL\n");
  554. len = 0;
  555. break;
  556. }
  557. port_status &= ~(1 << wValue);
  558. break;
  559. case RH_CLEAR_FEATURE | RH_CLASS:
  560. debug("RH_CLEAR_FEATURE | RH_CLASS\n");
  561. switch (wValue) {
  562. case RH_C_HUB_LOCAL_POWER:
  563. debug("C_HUB_LOCAL_POWER\n");
  564. len = 0;
  565. break;
  566. case RH_C_HUB_OVER_CURRENT:
  567. debug("C_HUB_OVER_CURRENT\n");
  568. len = 0;
  569. break;
  570. }
  571. port_status &= ~(1 << wValue);
  572. break;
  573. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  574. debug("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS\n");
  575. switch (wValue) {
  576. case RH_PORT_ENABLE:
  577. len = 0;
  578. break;
  579. case RH_PORT_SUSPEND:
  580. len = 0;
  581. break;
  582. case RH_PORT_POWER:
  583. len = 0;
  584. break;
  585. case RH_C_PORT_CONNECTION:
  586. len = 0;
  587. break;
  588. case RH_C_PORT_ENABLE:
  589. len = 0;
  590. break;
  591. case RH_C_PORT_SUSPEND:
  592. len = 0;
  593. break;
  594. case RH_C_PORT_OVER_CURRENT:
  595. len = 0;
  596. break;
  597. case RH_C_PORT_RESET:
  598. len = 0;
  599. break;
  600. default:
  601. debug("invalid wValue\n");
  602. stat = USB_ST_STALLED;
  603. }
  604. port_status &= ~(1 << wValue);
  605. break;
  606. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  607. debug("RH_SET_FEATURE | RH_OTHER | RH_CLASS\n");
  608. switch (wValue) {
  609. case RH_PORT_SUSPEND:
  610. len = 0;
  611. break;
  612. case RH_PORT_RESET:
  613. musb_port_reset(1);
  614. len = 0;
  615. break;
  616. case RH_PORT_POWER:
  617. len = 0;
  618. break;
  619. case RH_PORT_ENABLE:
  620. len = 0;
  621. break;
  622. default:
  623. debug("invalid wValue\n");
  624. stat = USB_ST_STALLED;
  625. }
  626. port_status |= 1 << wValue;
  627. break;
  628. case RH_SET_ADDRESS:
  629. debug("RH_SET_ADDRESS\n");
  630. rh_devnum = wValue;
  631. len = 0;
  632. break;
  633. case RH_GET_DESCRIPTOR:
  634. debug("RH_GET_DESCRIPTOR: %x, %d\n", wValue, wLength);
  635. switch (wValue) {
  636. case (USB_DT_DEVICE << 8): /* device descriptor */
  637. len = min_t(unsigned int,
  638. leni, min_t(unsigned int,
  639. sizeof(root_hub_dev_des),
  640. wLength));
  641. data_buf = root_hub_dev_des;
  642. break;
  643. case (USB_DT_CONFIG << 8): /* configuration descriptor */
  644. len = min_t(unsigned int,
  645. leni, min_t(unsigned int,
  646. sizeof(root_hub_config_des),
  647. wLength));
  648. data_buf = root_hub_config_des;
  649. break;
  650. case ((USB_DT_STRING << 8) | 0x00): /* string 0 descriptors */
  651. len = min_t(unsigned int,
  652. leni, min_t(unsigned int,
  653. sizeof(root_hub_str_index0),
  654. wLength));
  655. data_buf = root_hub_str_index0;
  656. break;
  657. case ((USB_DT_STRING << 8) | 0x01): /* string 1 descriptors */
  658. len = min_t(unsigned int,
  659. leni, min_t(unsigned int,
  660. sizeof(root_hub_str_index1),
  661. wLength));
  662. data_buf = root_hub_str_index1;
  663. break;
  664. default:
  665. debug("invalid wValue\n");
  666. stat = USB_ST_STALLED;
  667. }
  668. break;
  669. case RH_GET_DESCRIPTOR | RH_CLASS:
  670. debug("RH_GET_DESCRIPTOR | RH_CLASS\n");
  671. data_buf[0] = 0x09; /* min length; */
  672. data_buf[1] = 0x29;
  673. data_buf[2] = 0x1; /* 1 port */
  674. data_buf[3] = 0x01; /* per-port power switching */
  675. data_buf[3] |= 0x10; /* no overcurrent reporting */
  676. /* Corresponds to data_buf[4-7] */
  677. data_buf[4] = 0;
  678. data_buf[5] = 5;
  679. data_buf[6] = 0;
  680. data_buf[7] = 0x02;
  681. data_buf[8] = 0xff;
  682. len = min_t(unsigned int, leni,
  683. min_t(unsigned int, data_buf[0], wLength));
  684. break;
  685. case RH_GET_CONFIGURATION:
  686. debug("RH_GET_CONFIGURATION\n");
  687. *(__u8 *) data_buf = 0x01;
  688. len = 1;
  689. break;
  690. case RH_SET_CONFIGURATION:
  691. debug("RH_SET_CONFIGURATION\n");
  692. len = 0;
  693. break;
  694. default:
  695. debug("*** *** *** unsupported root hub command *** *** ***\n");
  696. stat = USB_ST_STALLED;
  697. }
  698. len = min_t(int, len, leni);
  699. if (buffer != data_buf)
  700. memcpy(buffer, data_buf, len);
  701. dev->act_len = len;
  702. dev->status = stat;
  703. debug("dev act_len %d, status %d\n", dev->act_len, dev->status);
  704. return stat;
  705. }
  706. static void musb_rh_init(void)
  707. {
  708. rh_devnum = 0;
  709. port_status = 0;
  710. }
  711. #else
  712. static void musb_rh_init(void) {}
  713. #endif
  714. /*
  715. * do a control transfer
  716. */
  717. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  718. int len, struct devrequest *setup)
  719. {
  720. int devnum = usb_pipedevice(pipe);
  721. u16 csr;
  722. u8 devspeed;
  723. #ifdef MUSB_NO_MULTIPOINT
  724. /* Control message is for the HUB? */
  725. if (devnum == rh_devnum)
  726. return musb_submit_rh_msg(dev, pipe, buffer, len, setup);
  727. #endif
  728. /* select control endpoint */
  729. writeb(MUSB_CONTROL_EP, &musbr->index);
  730. csr = readw(&musbr->txcsr);
  731. #ifndef MUSB_NO_MULTIPOINT
  732. /* target addr and (for multipoint) hub addr/port */
  733. writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr);
  734. writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr);
  735. #endif
  736. /* configure the hub address and the port number as required */
  737. devspeed = get_dev_speed(dev);
  738. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  739. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  740. config_hub_port(dev, MUSB_CONTROL_EP);
  741. writeb(devspeed << 6, &musbr->txtype);
  742. } else {
  743. writeb(musb_cfg.musb_speed << 6, &musbr->txtype);
  744. #ifndef MUSB_NO_MULTIPOINT
  745. writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr);
  746. writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport);
  747. writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr);
  748. writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport);
  749. #endif
  750. }
  751. /* Control transfer setup phase */
  752. if (ctrlreq_setup_phase(dev, setup) < 0)
  753. return 0;
  754. switch (setup->request) {
  755. case USB_REQ_GET_DESCRIPTOR:
  756. case USB_REQ_GET_CONFIGURATION:
  757. case USB_REQ_GET_INTERFACE:
  758. case USB_REQ_GET_STATUS:
  759. case USB_MSC_BBB_GET_MAX_LUN:
  760. /* control transfer in-data-phase */
  761. if (ctrlreq_in_data_phase(dev, len, buffer) < 0)
  762. return 0;
  763. /* control transfer out-status-phase */
  764. if (ctrlreq_out_status_phase(dev) < 0)
  765. return 0;
  766. break;
  767. case USB_REQ_SET_ADDRESS:
  768. case USB_REQ_SET_CONFIGURATION:
  769. case USB_REQ_SET_FEATURE:
  770. case USB_REQ_SET_INTERFACE:
  771. case USB_REQ_CLEAR_FEATURE:
  772. case USB_MSC_BBB_RESET:
  773. /* control transfer in status phase */
  774. if (ctrlreq_in_status_phase(dev) < 0)
  775. return 0;
  776. break;
  777. case USB_REQ_SET_DESCRIPTOR:
  778. /* control transfer out data phase */
  779. if (ctrlreq_out_data_phase(dev, len, buffer) < 0)
  780. return 0;
  781. /* control transfer in status phase */
  782. if (ctrlreq_in_status_phase(dev) < 0)
  783. return 0;
  784. break;
  785. default:
  786. /* unhandled control transfer */
  787. return -1;
  788. }
  789. dev->status = 0;
  790. dev->act_len = len;
  791. #ifdef MUSB_NO_MULTIPOINT
  792. /* Set device address to USB_FADDR register */
  793. if (setup->request == USB_REQ_SET_ADDRESS)
  794. writeb(dev->devnum, &musbr->faddr);
  795. #endif
  796. return len;
  797. }
  798. /*
  799. * do a bulk transfer
  800. */
  801. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  802. void *buffer, int len)
  803. {
  804. int dir_out = usb_pipeout(pipe);
  805. int ep = usb_pipeendpoint(pipe);
  806. #ifndef MUSB_NO_MULTIPOINT
  807. int devnum = usb_pipedevice(pipe);
  808. #endif
  809. u8 type;
  810. u16 csr;
  811. u32 txlen = 0;
  812. u32 nextlen = 0;
  813. u8 devspeed;
  814. /* select bulk endpoint */
  815. writeb(MUSB_BULK_EP, &musbr->index);
  816. #ifndef MUSB_NO_MULTIPOINT
  817. /* write the address of the device */
  818. if (dir_out)
  819. writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr);
  820. else
  821. writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr);
  822. #endif
  823. /* configure the hub address and the port number as required */
  824. devspeed = get_dev_speed(dev);
  825. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  826. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  827. /*
  828. * MUSB is in high speed and the destination device is full
  829. * speed device. So configure the hub address and port
  830. * address registers.
  831. */
  832. config_hub_port(dev, MUSB_BULK_EP);
  833. } else {
  834. #ifndef MUSB_NO_MULTIPOINT
  835. if (dir_out) {
  836. writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr);
  837. writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport);
  838. } else {
  839. writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr);
  840. writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport);
  841. }
  842. #endif
  843. devspeed = musb_cfg.musb_speed;
  844. }
  845. /* Write the saved toggle bit value */
  846. write_toggle(dev, ep, dir_out);
  847. if (dir_out) { /* bulk-out transfer */
  848. /* Program the TxType register */
  849. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  850. (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
  851. (ep & MUSB_TYPE_REMOTE_END);
  852. writeb(type, &musbr->txtype);
  853. /* Write maximum packet size to the TxMaxp register */
  854. writew(dev->epmaxpacketout[ep], &musbr->txmaxp);
  855. while (txlen < len) {
  856. nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ?
  857. (len-txlen) : dev->epmaxpacketout[ep];
  858. #ifdef CONFIG_USB_BLACKFIN
  859. /* Set the transfer data size */
  860. writew(nextlen, &musbr->txcount);
  861. #endif
  862. /* Write the data to the FIFO */
  863. write_fifo(MUSB_BULK_EP, nextlen,
  864. (void *)(((u8 *)buffer) + txlen));
  865. /* Set the TxPktRdy bit */
  866. csr = readw(&musbr->txcsr);
  867. writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
  868. /* Wait until the TxPktRdy bit is cleared */
  869. if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) {
  870. readw(&musbr->txcsr);
  871. usb_settoggle(dev, ep, dir_out,
  872. (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
  873. dev->act_len = txlen;
  874. return 0;
  875. }
  876. txlen += nextlen;
  877. }
  878. /* Keep a copy of the data toggle bit */
  879. csr = readw(&musbr->txcsr);
  880. usb_settoggle(dev, ep, dir_out,
  881. (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
  882. } else { /* bulk-in transfer */
  883. /* Write the saved toggle bit value */
  884. write_toggle(dev, ep, dir_out);
  885. /* Program the RxType register */
  886. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  887. (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) |
  888. (ep & MUSB_TYPE_REMOTE_END);
  889. writeb(type, &musbr->rxtype);
  890. /* Write the maximum packet size to the RxMaxp register */
  891. writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
  892. while (txlen < len) {
  893. nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
  894. (len-txlen) : dev->epmaxpacketin[ep];
  895. /* Set the ReqPkt bit */
  896. csr = readw(&musbr->rxcsr);
  897. writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
  898. /* Wait until the RxPktRdy bit is set */
  899. if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
  900. csr = readw(&musbr->rxcsr);
  901. usb_settoggle(dev, ep, dir_out,
  902. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  903. csr &= ~MUSB_RXCSR_RXPKTRDY;
  904. writew(csr, &musbr->rxcsr);
  905. dev->act_len = txlen;
  906. return 0;
  907. }
  908. /* Read the data from the FIFO */
  909. read_fifo(MUSB_BULK_EP, nextlen,
  910. (void *)(((u8 *)buffer) + txlen));
  911. /* Clear the RxPktRdy bit */
  912. csr = readw(&musbr->rxcsr);
  913. csr &= ~MUSB_RXCSR_RXPKTRDY;
  914. writew(csr, &musbr->rxcsr);
  915. txlen += nextlen;
  916. }
  917. /* Keep a copy of the data toggle bit */
  918. csr = readw(&musbr->rxcsr);
  919. usb_settoggle(dev, ep, dir_out,
  920. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  921. }
  922. /* bulk transfer is complete */
  923. dev->status = 0;
  924. dev->act_len = len;
  925. return 0;
  926. }
  927. /*
  928. * This function initializes the usb controller module.
  929. */
  930. int usb_lowlevel_init(void)
  931. {
  932. u8 power;
  933. u32 timeout;
  934. musb_rh_init();
  935. if (musb_platform_init() == -1)
  936. return -1;
  937. /* Configure all the endpoint FIFO's and start usb controller */
  938. musbr = musb_cfg.regs;
  939. musb_configure_ep(&epinfo[0],
  940. sizeof(epinfo) / sizeof(struct musb_epinfo));
  941. musb_start();
  942. /*
  943. * Wait until musb is enabled in host mode with a timeout. There
  944. * should be a usb device connected.
  945. */
  946. timeout = musb_cfg.timeout;
  947. while (timeout--)
  948. if (readb(&musbr->devctl) & MUSB_DEVCTL_HM)
  949. break;
  950. /* if musb core is not in host mode, then return */
  951. if (!timeout)
  952. return -1;
  953. /* start usb bus reset */
  954. power = readb(&musbr->power);
  955. writeb(power | MUSB_POWER_RESET, &musbr->power);
  956. /* After initiating a usb reset, wait for about 20ms to 30ms */
  957. udelay(30000);
  958. /* stop usb bus reset */
  959. power = readb(&musbr->power);
  960. power &= ~MUSB_POWER_RESET;
  961. writeb(power, &musbr->power);
  962. /* Determine if the connected device is a high/full/low speed device */
  963. musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ?
  964. MUSB_TYPE_SPEED_HIGH :
  965. ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ?
  966. MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW);
  967. return 0;
  968. }
  969. /*
  970. * This function stops the operation of the davinci usb module.
  971. */
  972. int usb_lowlevel_stop(void)
  973. {
  974. /* Reset the USB module */
  975. musb_platform_deinit();
  976. writeb(0, &musbr->devctl);
  977. return 0;
  978. }
  979. /*
  980. * This function supports usb interrupt transfers. Currently, usb interrupt
  981. * transfers are not supported.
  982. */
  983. int submit_int_msg(struct usb_device *dev, unsigned long pipe,
  984. void *buffer, int len, int interval)
  985. {
  986. int dir_out = usb_pipeout(pipe);
  987. int ep = usb_pipeendpoint(pipe);
  988. #ifndef MUSB_NO_MULTIPOINT
  989. int devnum = usb_pipedevice(pipe);
  990. #endif
  991. u8 type;
  992. u16 csr;
  993. u32 txlen = 0;
  994. u32 nextlen = 0;
  995. u8 devspeed;
  996. /* select interrupt endpoint */
  997. writeb(MUSB_INTR_EP, &musbr->index);
  998. #ifndef MUSB_NO_MULTIPOINT
  999. /* write the address of the device */
  1000. if (dir_out)
  1001. writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr);
  1002. else
  1003. writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr);
  1004. #endif
  1005. /* configure the hub address and the port number as required */
  1006. devspeed = get_dev_speed(dev);
  1007. if ((musb_ishighspeed()) && (dev->parent != NULL) &&
  1008. (devspeed != MUSB_TYPE_SPEED_HIGH)) {
  1009. /*
  1010. * MUSB is in high speed and the destination device is full
  1011. * speed device. So configure the hub address and port
  1012. * address registers.
  1013. */
  1014. config_hub_port(dev, MUSB_INTR_EP);
  1015. } else {
  1016. #ifndef MUSB_NO_MULTIPOINT
  1017. if (dir_out) {
  1018. writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr);
  1019. writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport);
  1020. } else {
  1021. writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr);
  1022. writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport);
  1023. }
  1024. #endif
  1025. devspeed = musb_cfg.musb_speed;
  1026. }
  1027. /* Write the saved toggle bit value */
  1028. write_toggle(dev, ep, dir_out);
  1029. if (!dir_out) { /* intrrupt-in transfer */
  1030. /* Write the saved toggle bit value */
  1031. write_toggle(dev, ep, dir_out);
  1032. writeb(interval, &musbr->rxinterval);
  1033. /* Program the RxType register */
  1034. type = (devspeed << MUSB_TYPE_SPEED_SHIFT) |
  1035. (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) |
  1036. (ep & MUSB_TYPE_REMOTE_END);
  1037. writeb(type, &musbr->rxtype);
  1038. /* Write the maximum packet size to the RxMaxp register */
  1039. writew(dev->epmaxpacketin[ep], &musbr->rxmaxp);
  1040. while (txlen < len) {
  1041. nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ?
  1042. (len-txlen) : dev->epmaxpacketin[ep];
  1043. /* Set the ReqPkt bit */
  1044. csr = readw(&musbr->rxcsr);
  1045. writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
  1046. /* Wait until the RxPktRdy bit is set */
  1047. if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
  1048. csr = readw(&musbr->rxcsr);
  1049. usb_settoggle(dev, ep, dir_out,
  1050. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  1051. csr &= ~MUSB_RXCSR_RXPKTRDY;
  1052. writew(csr, &musbr->rxcsr);
  1053. dev->act_len = txlen;
  1054. return 0;
  1055. }
  1056. /* Read the data from the FIFO */
  1057. read_fifo(MUSB_INTR_EP, nextlen,
  1058. (void *)(((u8 *)buffer) + txlen));
  1059. /* Clear the RxPktRdy bit */
  1060. csr = readw(&musbr->rxcsr);
  1061. csr &= ~MUSB_RXCSR_RXPKTRDY;
  1062. writew(csr, &musbr->rxcsr);
  1063. txlen += nextlen;
  1064. }
  1065. /* Keep a copy of the data toggle bit */
  1066. csr = readw(&musbr->rxcsr);
  1067. usb_settoggle(dev, ep, dir_out,
  1068. (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
  1069. }
  1070. /* interrupt transfer is complete */
  1071. dev->irq_status = 0;
  1072. dev->irq_act_len = len;
  1073. dev->irq_handle(dev);
  1074. dev->status = 0;
  1075. dev->act_len = len;
  1076. return 0;
  1077. }
  1078. #ifdef CONFIG_SYS_USB_EVENT_POLL
  1079. /*
  1080. * This function polls for USB keyboard data.
  1081. */
  1082. void usb_event_poll()
  1083. {
  1084. struct stdio_dev *dev;
  1085. struct usb_device *usb_kbd_dev;
  1086. struct usb_interface *iface;
  1087. struct usb_endpoint_descriptor *ep;
  1088. int pipe;
  1089. int maxp;
  1090. /* Get the pointer to USB Keyboard device pointer */
  1091. dev = stdio_get_by_name("usbkbd");
  1092. usb_kbd_dev = (struct usb_device *)dev->priv;
  1093. iface = &usb_kbd_dev->config.if_desc[0];
  1094. ep = &iface->ep_desc[0];
  1095. pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
  1096. /* Submit a interrupt transfer request */
  1097. maxp = usb_maxpacket(usb_kbd_dev, pipe);
  1098. usb_submit_int_msg(usb_kbd_dev, pipe, &new[0],
  1099. maxp > 8 ? 8 : maxp, ep->bInterval);
  1100. }
  1101. #endif /* CONFIG_SYS_USB_EVENT_POLL */