tqm8xx.c 19 KB

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  1. /*
  2. * (C) Copyright 2000-2008
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <hwconfig.h>
  25. #include <mpc8xx.h>
  26. #ifdef CONFIG_PS2MULT
  27. #include <ps2mult.h>
  28. #endif
  29. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  30. #include <libfdt.h>
  31. #endif
  32. extern flash_info_t flash_info[]; /* FLASH chips info */
  33. DECLARE_GLOBAL_DATA_PTR;
  34. static long int dram_size (long int, long int *, long int);
  35. #define _NOT_USED_ 0xFFFFFFFF
  36. /* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
  37. const uint sdram_table[] =
  38. {
  39. /*
  40. * Single Read. (Offset 0 in UPMA RAM)
  41. */
  42. 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
  43. 0x1FF5FC47, /* last */
  44. /*
  45. * SDRAM Initialization (offset 5 in UPMA RAM)
  46. *
  47. * This is no UPM entry point. The following definition uses
  48. * the remaining space to establish an initialization
  49. * sequence, which is executed by a RUN command.
  50. *
  51. */
  52. 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
  53. /*
  54. * Burst Read. (Offset 8 in UPMA RAM)
  55. */
  56. 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
  57. 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
  58. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  59. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  60. /*
  61. * Single Write. (Offset 18 in UPMA RAM)
  62. */
  63. 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
  64. 0x1FF5FC47, /* last */
  65. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66. /*
  67. * Burst Write. (Offset 20 in UPMA RAM)
  68. */
  69. 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
  70. 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
  71. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  72. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73. /*
  74. * Refresh (Offset 30 in UPMA RAM)
  75. */
  76. 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  77. 0xFFFFFC84, 0xFFFFFC07, /* last */
  78. _NOT_USED_, _NOT_USED_,
  79. _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  80. /*
  81. * Exception. (Offset 3c in UPMA RAM)
  82. */
  83. 0xFFFFFC07, /* last */
  84. _NOT_USED_, _NOT_USED_, _NOT_USED_,
  85. };
  86. /* ------------------------------------------------------------------------- */
  87. /*
  88. * Check Board Identity:
  89. *
  90. * Test TQ ID string (TQM8xx...)
  91. * If present, check for "L" type (no second DRAM bank),
  92. * otherwise "L" type is assumed as default.
  93. *
  94. * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
  95. */
  96. int checkboard (void)
  97. {
  98. char *s = getenv ("serial#");
  99. puts ("Board: ");
  100. if (!s || strncmp (s, "TQM8", 4)) {
  101. puts ("### No HW ID - assuming TQM8xxL\n");
  102. return (0);
  103. }
  104. if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
  105. gd->board_type = 'L';
  106. }
  107. if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
  108. gd->board_type = 'M';
  109. }
  110. if ((*(s + 6) == 'D')) { /* a TQM885D type */
  111. gd->board_type = 'D';
  112. }
  113. for (; *s; ++s) {
  114. if (*s == ' ')
  115. break;
  116. putc (*s);
  117. }
  118. #ifdef CONFIG_VIRTLAB2
  119. puts (" (Virtlab2)");
  120. #endif
  121. putc ('\n');
  122. return (0);
  123. }
  124. /* ------------------------------------------------------------------------- */
  125. phys_size_t initdram (int board_type)
  126. {
  127. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  128. volatile memctl8xx_t *memctl = &immap->im_memctl;
  129. long int size8, size9, size10;
  130. long int size_b0 = 0;
  131. long int size_b1 = 0;
  132. upmconfig (UPMA, (uint *) sdram_table,
  133. sizeof (sdram_table) / sizeof (uint));
  134. /*
  135. * Preliminary prescaler for refresh (depends on number of
  136. * banks): This value is selected for four cycles every 62.4 us
  137. * with two SDRAM banks or four cycles every 31.2 us with one
  138. * bank. It will be adjusted after memory sizing.
  139. */
  140. memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
  141. /*
  142. * The following value is used as an address (i.e. opcode) for
  143. * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
  144. * the port size is 32bit the SDRAM does NOT "see" the lower two
  145. * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
  146. * MICRON SDRAMs:
  147. * -> 0 00 010 0 010
  148. * | | | | +- Burst Length = 4
  149. * | | | +----- Burst Type = Sequential
  150. * | | +------- CAS Latency = 2
  151. * | +----------- Operating Mode = Standard
  152. * +-------------- Write Burst Mode = Programmed Burst Length
  153. */
  154. memctl->memc_mar = 0x00000088;
  155. /*
  156. * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
  157. * preliminary addresses - these have to be modified after the
  158. * SDRAM size has been determined.
  159. */
  160. memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
  161. memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
  162. #ifndef CONFIG_CAN_DRIVER
  163. if ((board_type != 'L') &&
  164. (board_type != 'M') &&
  165. (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
  166. memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
  167. memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
  168. }
  169. #endif /* CONFIG_CAN_DRIVER */
  170. memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
  171. udelay (200);
  172. /* perform SDRAM initializsation sequence */
  173. memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
  174. udelay (1);
  175. memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
  176. udelay (1);
  177. #ifndef CONFIG_CAN_DRIVER
  178. if ((board_type != 'L') &&
  179. (board_type != 'M') &&
  180. (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
  181. memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
  182. udelay (1);
  183. memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
  184. udelay (1);
  185. }
  186. #endif /* CONFIG_CAN_DRIVER */
  187. memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
  188. udelay (1000);
  189. /*
  190. * Check Bank 0 Memory Size for re-configuration
  191. *
  192. * try 8 column mode
  193. */
  194. size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
  195. debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
  196. udelay (1000);
  197. /*
  198. * try 9 column mode
  199. */
  200. size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
  201. debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
  202. udelay(1000);
  203. #if defined(CONFIG_SYS_MAMR_10COL)
  204. /*
  205. * try 10 column mode
  206. */
  207. size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
  208. debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
  209. #else
  210. size10 = 0;
  211. #endif /* CONFIG_SYS_MAMR_10COL */
  212. if ((size8 < size10) && (size9 < size10)) {
  213. size_b0 = size10;
  214. } else if ((size8 < size9) && (size10 < size9)) {
  215. size_b0 = size9;
  216. memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
  217. udelay (500);
  218. } else {
  219. size_b0 = size8;
  220. memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
  221. udelay (500);
  222. }
  223. debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
  224. #ifndef CONFIG_CAN_DRIVER
  225. if ((board_type != 'L') &&
  226. (board_type != 'M') &&
  227. (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
  228. /*
  229. * Check Bank 1 Memory Size
  230. * use current column settings
  231. * [9 column SDRAM may also be used in 8 column mode,
  232. * but then only half the real size will be used.]
  233. */
  234. size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
  235. SDRAM_MAX_SIZE);
  236. debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
  237. } else {
  238. size_b1 = 0;
  239. }
  240. #endif /* CONFIG_CAN_DRIVER */
  241. udelay (1000);
  242. /*
  243. * Adjust refresh rate depending on SDRAM type, both banks
  244. * For types > 128 MBit leave it at the current (fast) rate
  245. */
  246. if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
  247. /* reduce to 15.6 us (62.4 us / quad) */
  248. memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
  249. udelay (1000);
  250. }
  251. /*
  252. * Final mapping: map bigger bank first
  253. */
  254. if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
  255. memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  256. memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
  257. if (size_b0 > 0) {
  258. /*
  259. * Position Bank 0 immediately above Bank 1
  260. */
  261. memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  262. memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
  263. + size_b1;
  264. } else {
  265. unsigned long reg;
  266. /*
  267. * No bank 0
  268. *
  269. * invalidate bank
  270. */
  271. memctl->memc_br2 = 0;
  272. /* adjust refresh rate depending on SDRAM type, one bank */
  273. reg = memctl->memc_mptpr;
  274. reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
  275. memctl->memc_mptpr = reg;
  276. }
  277. } else { /* SDRAM Bank 0 is bigger - map first */
  278. memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  279. memctl->memc_br2 =
  280. (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
  281. if (size_b1 > 0) {
  282. /*
  283. * Position Bank 1 immediately above Bank 0
  284. */
  285. memctl->memc_or3 =
  286. ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
  287. memctl->memc_br3 =
  288. ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
  289. + size_b0;
  290. } else {
  291. unsigned long reg;
  292. #ifndef CONFIG_CAN_DRIVER
  293. /*
  294. * No bank 1
  295. *
  296. * invalidate bank
  297. */
  298. memctl->memc_br3 = 0;
  299. #endif /* CONFIG_CAN_DRIVER */
  300. /* adjust refresh rate depending on SDRAM type, one bank */
  301. reg = memctl->memc_mptpr;
  302. reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
  303. memctl->memc_mptpr = reg;
  304. }
  305. }
  306. udelay (10000);
  307. #ifdef CONFIG_CAN_DRIVER
  308. /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
  309. /* Initialize OR3 / BR3 */
  310. memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
  311. memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
  312. /* Initialize MBMR */
  313. memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
  314. /* Initialize UPMB for CAN: single read */
  315. memctl->memc_mdr = 0xFFFFCC04;
  316. memctl->memc_mcr = 0x0100 | UPMB;
  317. memctl->memc_mdr = 0x0FFFD004;
  318. memctl->memc_mcr = 0x0101 | UPMB;
  319. memctl->memc_mdr = 0x0FFFC000;
  320. memctl->memc_mcr = 0x0102 | UPMB;
  321. memctl->memc_mdr = 0x3FFFC004;
  322. memctl->memc_mcr = 0x0103 | UPMB;
  323. memctl->memc_mdr = 0xFFFFDC07;
  324. memctl->memc_mcr = 0x0104 | UPMB;
  325. /* Initialize UPMB for CAN: single write */
  326. memctl->memc_mdr = 0xFFFCCC04;
  327. memctl->memc_mcr = 0x0118 | UPMB;
  328. memctl->memc_mdr = 0xCFFCDC04;
  329. memctl->memc_mcr = 0x0119 | UPMB;
  330. memctl->memc_mdr = 0x3FFCC000;
  331. memctl->memc_mcr = 0x011A | UPMB;
  332. memctl->memc_mdr = 0xFFFCC004;
  333. memctl->memc_mcr = 0x011B | UPMB;
  334. memctl->memc_mdr = 0xFFFDC405;
  335. memctl->memc_mcr = 0x011C | UPMB;
  336. #endif /* CONFIG_CAN_DRIVER */
  337. #ifdef CONFIG_ISP1362_USB
  338. /* Initialize OR5 / BR5 */
  339. memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
  340. memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
  341. #endif /* CONFIG_ISP1362_USB */
  342. return (size_b0 + size_b1);
  343. }
  344. /* ------------------------------------------------------------------------- */
  345. /*
  346. * Check memory range for valid RAM. A simple memory test determines
  347. * the actually available RAM size between addresses `base' and
  348. * `base + maxsize'. Some (not all) hardware errors are detected:
  349. * - short between address lines
  350. * - short between data lines
  351. */
  352. static long int dram_size (long int mamr_value, long int *base, long int maxsize)
  353. {
  354. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  355. volatile memctl8xx_t *memctl = &immap->im_memctl;
  356. memctl->memc_mamr = mamr_value;
  357. return (get_ram_size(base, maxsize));
  358. }
  359. /* ------------------------------------------------------------------------- */
  360. #ifdef CONFIG_MISC_INIT_R
  361. extern void load_sernum_ethaddr(void);
  362. int misc_init_r (void)
  363. {
  364. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  365. volatile memctl8xx_t *memctl = &immap->im_memctl;
  366. load_sernum_ethaddr();
  367. #ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
  368. int scy, trlx, flash_or_timing, clk_diff;
  369. scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
  370. if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
  371. trlx = OR_TRLX;
  372. scy *= 2;
  373. } else {
  374. trlx = 0;
  375. }
  376. /*
  377. * We assume that each 10MHz of bus clock require 1-clk SCY
  378. * adjustment.
  379. */
  380. clk_diff = (gd->bus_clk / 1000000) - 50;
  381. /*
  382. * We need proper rounding here. This is what the "+5" and "-5"
  383. * are here for.
  384. */
  385. if (clk_diff >= 0)
  386. scy += (clk_diff + 5) / 10;
  387. else
  388. scy += (clk_diff - 5) / 10;
  389. /*
  390. * For bus frequencies above 50MHz, we want to use relaxed timing
  391. * (OR_TRLX).
  392. */
  393. if (gd->bus_clk >= 50000000)
  394. trlx = OR_TRLX;
  395. else
  396. trlx = 0;
  397. if (trlx)
  398. scy /= 2;
  399. if (scy > 0xf)
  400. scy = 0xf;
  401. if (scy < 1)
  402. scy = 1;
  403. flash_or_timing = (scy << 4) | trlx |
  404. (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
  405. memctl->memc_or0 =
  406. flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
  407. #else
  408. memctl->memc_or0 =
  409. CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
  410. #endif
  411. memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
  412. debug ("## BR0: 0x%08x OR0: 0x%08x\n",
  413. memctl->memc_br0, memctl->memc_or0);
  414. if (flash_info[1].size) {
  415. #ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
  416. memctl->memc_or1 = flash_or_timing |
  417. (-flash_info[1].size & 0xFFFF8000);
  418. #else
  419. memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
  420. (-flash_info[1].size & 0xFFFF8000);
  421. #endif
  422. memctl->memc_br1 =
  423. ((CONFIG_SYS_FLASH_BASE +
  424. flash_info[0].
  425. size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
  426. debug ("## BR1: 0x%08x OR1: 0x%08x\n",
  427. memctl->memc_br1, memctl->memc_or1);
  428. } else {
  429. memctl->memc_br1 = 0; /* invalidate bank */
  430. debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
  431. memctl->memc_br1, memctl->memc_or1);
  432. }
  433. # ifdef CONFIG_IDE_LED
  434. /* Configure PA15 as output port */
  435. immap->im_ioport.iop_padir |= 0x0001;
  436. immap->im_ioport.iop_paodr |= 0x0001;
  437. immap->im_ioport.iop_papar &= ~0x0001;
  438. immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
  439. # endif
  440. #ifdef CONFIG_NSCU
  441. /* wake up ethernet module */
  442. immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
  443. immap->im_ioport.iop_pcdir |= 0x0004; /* output */
  444. immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
  445. immap->im_ioport.iop_pcdat |= 0x0004; /* enable */
  446. #endif /* CONFIG_NSCU */
  447. return (0);
  448. }
  449. #endif /* CONFIG_MISC_INIT_R */
  450. # ifdef CONFIG_IDE_LED
  451. void ide_led (uchar led, uchar status)
  452. {
  453. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  454. /* We have one led for both pcmcia slots */
  455. if (status) { /* led on */
  456. immap->im_ioport.iop_padat |= 0x0001;
  457. } else {
  458. immap->im_ioport.iop_padat &= ~0x0001;
  459. }
  460. }
  461. # endif
  462. #ifdef CONFIG_LCD_INFO
  463. #include <lcd.h>
  464. #include <version.h>
  465. #include <timestamp.h>
  466. void lcd_show_board_info(void)
  467. {
  468. char temp[32];
  469. lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
  470. lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
  471. lcd_printf (" Wolfgang DENK, wd@denx.de\n");
  472. #ifdef CONFIG_LCD_INFO_BELOW_LOGO
  473. lcd_printf ("MPC823 CPU at %s MHz\n",
  474. strmhz(temp, gd->cpu_clk));
  475. lcd_printf (" %ld MB RAM, %ld MB Flash\n",
  476. gd->ram_size >> 20,
  477. gd->bd->bi_flashsize >> 20 );
  478. #else
  479. /* leave one blank line */
  480. lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
  481. strmhz(temp, gd->cpu_clk),
  482. gd->ram_size >> 20,
  483. gd->bd->bi_flashsize >> 20 );
  484. #endif /* CONFIG_LCD_INFO_BELOW_LOGO */
  485. }
  486. #endif /* CONFIG_LCD_INFO */
  487. /*
  488. * Device Tree Support
  489. */
  490. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  491. int fdt_set_node_and_value (void *blob,
  492. char *nodename,
  493. char *regname,
  494. void *var,
  495. int size)
  496. {
  497. int ret = 0;
  498. int nodeoffset = 0;
  499. nodeoffset = fdt_path_offset (blob, nodename);
  500. if (nodeoffset >= 0) {
  501. ret = fdt_setprop (blob, nodeoffset, regname, var,
  502. size);
  503. if (ret < 0) {
  504. printf("ft_blob_update(): "
  505. "cannot set %s/%s property; err: %s\n",
  506. nodename, regname, fdt_strerror (ret));
  507. }
  508. } else {
  509. printf("ft_blob_update(): "
  510. "cannot find %s node err:%s\n",
  511. nodename, fdt_strerror (nodeoffset));
  512. }
  513. return ret;
  514. }
  515. int fdt_del_node_name (void *blob, char *nodename)
  516. {
  517. int ret = 0;
  518. int nodeoffset = 0;
  519. nodeoffset = fdt_path_offset (blob, nodename);
  520. if (nodeoffset >= 0) {
  521. ret = fdt_del_node (blob, nodeoffset);
  522. if (ret < 0) {
  523. printf("%s: cannot delete %s; err: %s\n",
  524. __func__, nodename, fdt_strerror (ret));
  525. }
  526. } else {
  527. printf("%s: cannot find %s node err:%s\n",
  528. __func__, nodename, fdt_strerror (nodeoffset));
  529. }
  530. return ret;
  531. }
  532. int fdt_del_prop_name (void *blob, char *nodename, char *propname)
  533. {
  534. int ret = 0;
  535. int nodeoffset = 0;
  536. nodeoffset = fdt_path_offset (blob, nodename);
  537. if (nodeoffset >= 0) {
  538. ret = fdt_delprop (blob, nodeoffset, propname);
  539. if (ret < 0) {
  540. printf("%s: cannot delete %s %s; err: %s\n",
  541. __func__, nodename, propname,
  542. fdt_strerror (ret));
  543. }
  544. } else {
  545. printf("%s: cannot find %s node err:%s\n",
  546. __func__, nodename, fdt_strerror (nodeoffset));
  547. }
  548. return ret;
  549. }
  550. /*
  551. * update "brg" property in the blob
  552. */
  553. void ft_blob_update (void *blob, bd_t *bd)
  554. {
  555. uchar enetaddr[6];
  556. ulong brg_data = 0;
  557. /* BRG */
  558. brg_data = cpu_to_be32(bd->bi_busfreq);
  559. fdt_set_node_and_value(blob,
  560. "/soc/cpm", "brg-frequency",
  561. &brg_data, sizeof(brg_data));
  562. /* MAC addr */
  563. if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
  564. fdt_set_node_and_value(blob,
  565. "ethernet0", "local-mac-address",
  566. enetaddr, sizeof(u8) * 6);
  567. }
  568. if (hwconfig_arg_cmp("fec", "off")) {
  569. /* no FEC on this plattform, delete DTS nodes */
  570. fdt_del_node_name (blob, "ethernet1");
  571. fdt_del_node_name (blob, "mdio1");
  572. /* also the aliases entries */
  573. fdt_del_prop_name (blob, "/aliases", "ethernet1");
  574. fdt_del_prop_name (blob, "/aliases", "mdio1");
  575. } else {
  576. /* adjust local-mac-address for FEC ethernet */
  577. if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
  578. fdt_set_node_and_value(blob,
  579. "ethernet1", "local-mac-address",
  580. enetaddr, sizeof(u8) * 6);
  581. }
  582. }
  583. }
  584. void ft_board_setup(void *blob, bd_t *bd)
  585. {
  586. ft_cpu_setup(blob, bd);
  587. ft_blob_update(blob, bd);
  588. }
  589. #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
  590. /* ---------------------------------------------------------------------------- */
  591. /* TK885D specific initializaion */
  592. /* ---------------------------------------------------------------------------- */
  593. #ifdef CONFIG_TK885D
  594. #include <miiphy.h>
  595. int last_stage_init(void)
  596. {
  597. const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
  598. unsigned short reg;
  599. int ret, i = 100;
  600. char *s;
  601. mii_init();
  602. /* Without this delay 0xff is read from the UART buffer later in
  603. * abortboot() and autoboot is aborted */
  604. udelay(10000);
  605. while (tstc() && i--)
  606. (void)getc();
  607. /* Check if auto-negotiation is prohibited */
  608. s = getenv("phy_auto_nego");
  609. if (!s || !strcmp(s, "on"))
  610. /* Nothing to do - autonegotiation by default */
  611. return 0;
  612. for (i = 0; i < 2; i++) {
  613. ret = miiphy_read("FEC", phy[i], PHY_BMCR, &reg);
  614. if (ret) {
  615. printf("Cannot read BMCR on PHY %d\n", phy[i]);
  616. return 0;
  617. }
  618. /* Auto-negotiation off, hard set full duplex, 100Mbps */
  619. ret = miiphy_write("FEC", phy[i],
  620. PHY_BMCR, (reg | PHY_BMCR_100MB |
  621. PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON);
  622. if (ret) {
  623. printf("Cannot write BMCR on PHY %d\n", phy[i]);
  624. return 0;
  625. }
  626. }
  627. return 0;
  628. }
  629. #endif