uc101.c 10 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4. *
  5. * (C) Copyright 2003-2004
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * (C) Copyright 2004
  9. * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  10. *
  11. * (C) Copyright 2004
  12. * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. */
  32. #include <common.h>
  33. #include <fdt_support.h>
  34. #include <mpc5xxx.h>
  35. #include <pci.h>
  36. #include <malloc.h>
  37. /* some SIMPLE GPIO Pins */
  38. #define GPIO_USB_8 (31-12)
  39. #define GPIO_USB_7 (31-13)
  40. #define GPIO_USB_6 (31-14)
  41. #define GPIO_USB_0 (31-15)
  42. #define GPIO_PSC3_7 (31-18)
  43. #define GPIO_PSC3_6 (31-19)
  44. #define GPIO_PSC3_1 (31-22)
  45. #define GPIO_PSC3_0 (31-23)
  46. /* some simple Interrupt GPIO Pins */
  47. #define GPIO_PSC3_8 2
  48. #define GPIO_USB1_9 3
  49. #define GPT_OUT_0 0x00000027
  50. #define GPT_OUT_1 0x00000037
  51. #define GPT_DISABLE 0x00000000 /* GPT pin disabled */
  52. #define GP_SIMP_ENABLE_O(n, v) {pgpio->simple_dvo |= (v << n); \
  53. pgpio->simple_ddr |= (1 << n); \
  54. pgpio->simple_gpioe |= (1 << n); \
  55. }
  56. #define GP_SIMP_ENABLE_I(n) { pgpio->simple_ddr |= ~(1 << n); \
  57. pgpio->simple_gpioe |= (1 << n); \
  58. }
  59. #define GP_SIMP_SET_O(n, v) (pgpio->simple_dvo = v ? \
  60. (pgpio->simple_dvo | (1 << n)) : \
  61. (pgpio->simple_dvo & ~(1 << n)) )
  62. #define GP_SIMP_GET_O(n) ((pgpio->simple_dvo >> n) & 1)
  63. #define GP_SIMP_GET_I(n) ((pgpio->simple_ival >> n) & 1)
  64. #define GP_SINT_SET_O(n, v) (pgpio->sint_dvo = v ? \
  65. (pgpio->sint_dvo | (1 << n)) : \
  66. (pgpio->sint_dvo & ~(1 << n)) )
  67. #define GP_SINT_ENABLE_O(n, v) {pgpio->sint_ode &= ~(1 << n); \
  68. pgpio->sint_ddr |= (1 << n); \
  69. GP_SINT_SET_O(n, v); \
  70. pgpio->sint_gpioe |= (1 << n); \
  71. }
  72. #define GP_SINT_ENABLE_I(n) { pgpio->sint_ddr |= ~(1 << n); \
  73. pgpio->sint_gpioe |= (1 << n); \
  74. }
  75. #define GP_SINT_GET_O(n) ((pgpio->sint_ival >> n) & 1)
  76. #define GP_SINT_GET_I(n) ((pgpio-ntt_ival >> n) & 1)
  77. #define GP_TIMER_ENABLE_O(n, v) ( \
  78. ((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr = v ? \
  79. GPT_OUT_1 : \
  80. GPT_OUT_0 )
  81. #define GP_TIMER_SET_O(n, v) GP_TIMER_ENABLE_O(n, v)
  82. #define GP_TIMER_GET_O(n, v) ( \
  83. (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->emsr & 0x10) >> 4)
  84. #define GP_TIMER_GET_I(n, v) ( \
  85. (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
  86. #ifndef CONFIG_SYS_RAMBOOT
  87. static void sdram_start (int hi_addr)
  88. {
  89. long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  90. /* unlock mode register */
  91. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  92. __asm__ volatile ("sync");
  93. /* precharge all banks */
  94. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  95. __asm__ volatile ("sync");
  96. #if SDRAM_DDR
  97. /* set mode register: extended mode */
  98. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  99. __asm__ volatile ("sync");
  100. /* set mode register: reset DLL */
  101. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  102. __asm__ volatile ("sync");
  103. #endif
  104. /* precharge all banks */
  105. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
  106. __asm__ volatile ("sync");
  107. /* auto refresh */
  108. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
  109. __asm__ volatile ("sync");
  110. /* set mode register */
  111. *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  112. __asm__ volatile ("sync");
  113. /* normal operation */
  114. *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  115. __asm__ volatile ("sync");
  116. }
  117. #endif
  118. /*
  119. * ATTENTION: Although partially referenced initdram does NOT make real use
  120. * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  121. * is something else than 0x00000000.
  122. */
  123. phys_size_t initdram (int board_type)
  124. {
  125. ulong dramsize = 0;
  126. #ifndef CONFIG_SYS_RAMBOOT
  127. ulong test1, test2;
  128. /* setup SDRAM chip selects */
  129. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
  130. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
  131. __asm__ volatile ("sync");
  132. /* setup config registers */
  133. *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
  134. *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
  135. __asm__ volatile ("sync");
  136. #if SDRAM_DDR
  137. /* set tap delay */
  138. *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
  139. __asm__ volatile ("sync");
  140. #endif
  141. /* find RAM size using SDRAM CS0 only */
  142. sdram_start(0);
  143. test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
  144. sdram_start(1);
  145. test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
  146. if (test1 > test2) {
  147. sdram_start(0);
  148. dramsize = test1;
  149. } else {
  150. dramsize = test2;
  151. }
  152. /* memory smaller than 1MB is impossible */
  153. if (dramsize < (1 << 20)) {
  154. dramsize = 0;
  155. }
  156. /* set SDRAM CS0 size according to the amount of RAM found */
  157. if (dramsize > 0) {
  158. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
  159. __builtin_ffs(dramsize >> 20) - 1;
  160. } else {
  161. *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
  162. }
  163. *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
  164. #else /* CONFIG_SYS_RAMBOOT */
  165. /* retrieve size of memory connected to SDRAM CS0 */
  166. dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
  167. if (dramsize >= 0x13) {
  168. dramsize = (1 << (dramsize - 0x13)) << 20;
  169. } else {
  170. dramsize = 0;
  171. }
  172. /* retrieve size of memory connected to SDRAM CS1 */
  173. dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
  174. if (dramsize2 >= 0x13) {
  175. dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
  176. } else {
  177. dramsize2 = 0;
  178. }
  179. #endif /* CONFIG_SYS_RAMBOOT */
  180. /* return dramsize + dramsize2; */
  181. return dramsize;
  182. }
  183. int checkboard (void)
  184. {
  185. puts ("Board: MAN UC101\n");
  186. /* clear the Display */
  187. *(char *)(CONFIG_SYS_DISP_CWORD) = 0x80;
  188. return 0;
  189. }
  190. static void init_ports (void)
  191. {
  192. volatile struct mpc5xxx_gpio *pgpio =
  193. (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
  194. GP_SIMP_ENABLE_I(GPIO_USB_8); /* HEX Bit 3 */
  195. GP_SIMP_ENABLE_I(GPIO_USB_7); /* HEX Bit 2 */
  196. GP_SIMP_ENABLE_I(GPIO_USB_6); /* HEX Bit 1 */
  197. GP_SIMP_ENABLE_I(GPIO_USB_0); /* HEX Bit 0 */
  198. GP_SIMP_ENABLE_I(GPIO_PSC3_0); /* Switch Menue A */
  199. GP_SIMP_ENABLE_I(GPIO_PSC3_1); /* Switch Menue B */
  200. GP_SIMP_ENABLE_I(GPIO_PSC3_6); /* Switch Cold_Warm */
  201. GP_SIMP_ENABLE_I(GPIO_PSC3_7); /* Switch Restart */
  202. GP_SINT_ENABLE_O(GPIO_PSC3_8, 0); /* LED H2 */
  203. GP_SINT_ENABLE_O(GPIO_USB1_9, 0); /* LED H3 */
  204. GP_TIMER_ENABLE_O(4, 0); /* LED H4 */
  205. GP_TIMER_ENABLE_O(5, 0); /* LED H5 */
  206. GP_TIMER_ENABLE_O(3, 0); /* LED HB */
  207. GP_TIMER_ENABLE_O(1, 0); /* RES_COLDSTART */
  208. }
  209. #ifdef CONFIG_PREBOOT
  210. static uchar kbd_magic_prefix[] = "key_magic";
  211. static uchar kbd_command_prefix[] = "key_cmd";
  212. struct kbd_data_t {
  213. char s1;
  214. };
  215. struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
  216. {
  217. volatile struct mpc5xxx_gpio *pgpio =
  218. (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
  219. kbd_data->s1 = GP_SIMP_GET_I(GPIO_USB_8) << 3 | \
  220. GP_SIMP_GET_I(GPIO_USB_7) << 2 | \
  221. GP_SIMP_GET_I(GPIO_USB_6) << 1 | \
  222. GP_SIMP_GET_I(GPIO_USB_0) << 0;
  223. return kbd_data;
  224. }
  225. static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
  226. {
  227. char s1 = str[0];
  228. if (s1 >= '0' && s1 <= '9')
  229. s1 -= '0';
  230. else if (s1 >= 'a' && s1 <= 'f')
  231. s1 = s1 - 'a' + 10;
  232. else if (s1 >= 'A' && s1 <= 'F')
  233. s1 = s1 - 'A' + 10;
  234. else
  235. return -1;
  236. if (s1 != kbd_data->s1) return -1;
  237. return 0;
  238. }
  239. static char *key_match (const struct kbd_data_t *kbd_data)
  240. {
  241. char magic[sizeof (kbd_magic_prefix) + 1];
  242. char *suffix;
  243. char *kbd_magic_keys;
  244. /*
  245. * The following string defines the characters that can be appended
  246. * to "key_magic" to form the names of environment variables that
  247. * hold "magic" key codes, i. e. such key codes that can cause
  248. * pre-boot actions. If the string is empty (""), then only
  249. * "key_magic" is checked (old behaviour); the string "125" causes
  250. * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
  251. */
  252. if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
  253. kbd_magic_keys = "";
  254. /* loop over all magic keys;
  255. * use '\0' suffix in case of empty string
  256. */
  257. for (suffix = kbd_magic_keys; *suffix ||
  258. suffix == kbd_magic_keys; ++suffix) {
  259. sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
  260. if (compare_magic(kbd_data, getenv(magic)) == 0) {
  261. char cmd_name[sizeof (kbd_command_prefix) + 1];
  262. char *cmd;
  263. sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
  264. cmd = getenv (cmd_name);
  265. return (cmd);
  266. }
  267. }
  268. return (NULL);
  269. }
  270. #endif /* CONFIG_PREBOOT */
  271. int misc_init_r (void)
  272. {
  273. /* Init the I/O ports */
  274. init_ports ();
  275. #ifdef CONFIG_PREBOOT
  276. struct kbd_data_t kbd_data;
  277. /* Decode keys */
  278. char *str = strdup (key_match (get_keys (&kbd_data)));
  279. /* Set or delete definition */
  280. setenv ("preboot", str);
  281. free (str);
  282. #endif /* CONFIG_PREBOOT */
  283. return 0;
  284. }
  285. int board_early_init_r (void)
  286. {
  287. *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
  288. *(vu_long *)MPC5XXX_BOOTCS_START =
  289. *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
  290. *(vu_long *)MPC5XXX_BOOTCS_STOP =
  291. *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
  292. /* Interbus enable it here ?? */
  293. *(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
  294. return 0;
  295. }
  296. #ifdef CONFIG_PCI
  297. static struct pci_controller hose;
  298. extern void pci_mpc5xxx_init(struct pci_controller *);
  299. void pci_init_board(void)
  300. {
  301. pci_mpc5xxx_init(&hose);
  302. }
  303. #endif
  304. #if defined(CONFIG_HW_WATCHDOG)
  305. void hw_watchdog_reset(void)
  306. {
  307. /* Trigger HW Watchdog with TIMER_0 */
  308. *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_1;
  309. *(vu_long *)MPC5XXX_GPT0_ENABLE = GPT_OUT_0;
  310. }
  311. #endif
  312. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  313. void ft_board_setup(void *blob, bd_t *bd)
  314. {
  315. ft_cpu_setup(blob, bd);
  316. }
  317. #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */